1 /* $NetBSD: df_3_6_sh_mask.h,v 1.2 2021/12/18 23:45:13 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _df_3_6_SH_MASK_HEADER 24 #define _df_3_6_SH_MASK_HEADER 25 26 /* FabricConfigAccessControl */ 27 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0 28 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1 29 #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10 30 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L 31 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L 32 #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L 33 34 /* DF_PIE_AON0_DfGlobalClkGater */ 35 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0 36 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL 37 38 /* DF_CS_UMC_AON0_DfGlobalCtrl */ 39 #define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K__SHIFT 0x14 40 #define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M__SHIFT 0x15 41 #define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G__SHIFT 0x16 42 #define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K_MASK 0x00100000L 43 #define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M_MASK 0x00200000L 44 #define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G_MASK 0x00400000L 45 46 /* DF_CS_AON0_DramBaseAddress0 */ 47 #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 48 #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 49 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2 50 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x9 51 #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 52 #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 53 #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 54 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL 55 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L 56 #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 57 58 //DF_CS_UMC_AON0_DramLimitAddress0 59 #define DF_CS_UMC_AON0_DramLimitAddress0__DstFabricID__SHIFT 0x0 60 #define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO__SHIFT 0xa 61 #define DF_CS_UMC_AON0_DramLimitAddress0__DramLimitAddr__SHIFT 0xc 62 #define DF_CS_UMC_AON0_DramLimitAddress0__DstFabricID_MASK 0x000003FFL 63 #define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO_MASK 0x00000400L 64 #define DF_CS_UMC_AON0_DramLimitAddress0__DramLimitAddr_MASK 0xFFFFF000L 65 66 #endif 67
Indexes created Sun Oct 12 09:09:55 GMT 2025