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    Searched refs:DIG_BE_CNTL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_link_encoder.c 461 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
569 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
886 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
890 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
895 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
899 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
903 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
1330 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1337 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1412 REG_GET(DIG_BE_CNTL, DIG_MODE, &value)
    [all...]
dcn10_link_encoder.h 45 SRI(DIG_BE_CNTL, DIG, id), \
85 uint32_t DIG_BE_CNTL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_link_encoder.c 581 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
892 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
896 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
901 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
905 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
909 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
1363 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1370 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
dce_link_encoder.h 53 SRI(DIG_BE_CNTL, DIG, id), \
133 uint32_t DIG_BE_CNTL;

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