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    Searched refs:DIG_START (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c 500 /* set DIG_START to 0x1 to reset FIFO */
501 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
506 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 170 SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
252 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
448 uint8_t DIG_START;
579 uint32_t DIG_START;
amdgpu_dce_stream_encoder.c 1012 /* set DIG_START to 0x1 to resync FIFO */
1014 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 222 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
412 type DIG_START;\
amdgpu_dcn10_stream_encoder.c 976 /* set DIG_START to 0x1 to resync FIFO */
978 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

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