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    Searched refs:DISPCLK (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_mode_vba_20v2.c 70 double DISPCLK,
99 double DISPCLK,
477 double DISPCLK,
525 if (DPPCLK == 0.0 || DISPCLK == 0.0)
528 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
549 double DISPCLK,
615 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
632 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
1160 // dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation
2034 / mode_lib->vba.DISPCLK;
    [all...]
amdgpu_display_mode_vba_20.c 64 double DISPCLK,
447 double DISPCLK,
533 if (DPPCLK == 0.0 || DISPCLK == 0.0)
536 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
552 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
569 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
1100 // dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation
1998 / mode_lib->vba.DISPCLK;
2017 / mode_lib->vba.DISPCLK);
2099 mode_lib->vba.DISPCLK,
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_mode_vba_21.c 48 double DISPCLK;
742 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
746 + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
761 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK);
778 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / myPipe->DISPCLK;
1479 // DISPCLK and DPPCLK Calculation
2055 / mode_lib->vba.DISPCLK;
2074 / mode_lib->vba.DISPCLK);
2141 myPipe.DISPCLK = mode_lib->vba.DISPCLK;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_display_mode_vba.c 837 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz;
839 mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz;
display_mode_vba.h 271 double DISPCLK;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_navi10_ppt.c 147 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
amdgpu_vega20_ppt.c 165 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
855 /* dispclk */
862 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 289 /*Extra state, no dispclk ramping*/
2537 /* Adjust dppclk when split is forced, do not bother with dispclk */
2787 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;

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