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    Searched refs:DKL_PLL_DIV0 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 3238 hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
3435 val = I915_READ(DKL_PLL_DIV0(tc_port));
3441 I915_WRITE(DKL_PLL_DIV0(tc_port), val);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 10291 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \

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