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    Searched refs:DMAC_DESC_DST (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/arch/arm/s3c2xx0/
s3c2440_dma.c 204 if (dx->dx_desc[DMAC_DESC_DST].xd_increment) {
205 dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs--;
206 if (dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs == 0) {
209 dxs->dxs_segs[DMAC_DESC_DST].ds_curseg++;
385 dxs->dxs_segs[DMAC_DESC_DST].ds_curseg = dx->dx_desc[DMAC_DESC_DST].xd_dma_segs;
386 dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs = dx->dx_desc[DMAC_DESC_DST].xd_nsegs;
476 DPRINTF(("Dest. address: 0x%x\n", (unsigned)dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_addr));
493 dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_addr)
    [all...]
s3c2440_i2s.c 411 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;
412 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE;
413 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
414 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &i2s->sc_dr;
478 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;
479 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE;
480 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = buf->i2b_dmamap->dm_nsegs;
481 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = buf->i2b_dmamap->dm_segs;
s3c2440_dma.h 108 #define DMAC_DESC_DST 1
s3c2440_sdi.c 455 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;
456 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE;
457 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = cmd->c_dmamap->dm_nsegs;
458 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = cmd->c_dmamap->dm_segs;
486 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;
487 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE;
488 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
489 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
  /src/sys/arch/arm/xscale/
pxa2x0_dmac.h 147 #define DMAC_DESC_DST 1
pxa2x0_i2s.c 346 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
347 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
348 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
396 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
397 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = p->nsegs;
398 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = p->segs;
pxa2x0_dmac.c 145 #define ds_dst_addr_hold ds_xfer.dxs_desc[DMAC_DESC_DST].xd_addr_hold
147 #define ds_dst_burst ds_xfer.dxs_desc[DMAC_DESC_DST].xd_burst_size
149 #define ds_dst_dma_segs ds_xfer.dxs_desc[DMAC_DESC_DST].xd_dma_segs
151 #define ds_dst_nsegs ds_xfer.dxs_desc[DMAC_DESC_DST].xd_nsegs
838 dst = &dxs->dxs_desc[DMAC_DESC_DST];
850 if ((err = dmac_init_desc(&dxs->dxs_segs[DMAC_DESC_DST], dst, &size,
1043 dst_ds = &dxs->dxs_segs[DMAC_DESC_DST];
1045 dst_xd = &dxs->dxs_desc[DMAC_DESC_DST];
1258 dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs == 0 ||
pxa2x0_ac97.c 788 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
789 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
790 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
841 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
842 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;
843 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;
pxa2x0_mci.c 271 sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
289 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
290 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
291 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr;
635 dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST];

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