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    Searched refs:DMAC_DESC_SRC (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/arch/arm/s3c2xx0/
s3c2440_dma.c 196 if (dx->dx_desc[DMAC_DESC_SRC].xd_increment) {
197 dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs--;
198 if (dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs == 0) {
201 dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg++;
383 dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg = dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs;
384 dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs = dx->dx_desc[DMAC_DESC_SRC].xd_nsegs;
473 dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_addr);
475 DPRINTF(("Source address: 0x%x\n", (unsigned)dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_addr))
    [all...]
s3c2440_i2s.c 416 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;
417 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE;
418 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = buf->i2b_dmamap->dm_nsegs;
419 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = buf->i2b_dmamap->dm_segs;
473 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;
474 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE;
475 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
476 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &i2s->sc_dr;
s3c2440_dma.h 107 #define DMAC_DESC_SRC 0
s3c2440_sdi.c 450 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;
451 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE;
452 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
453 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
491 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;
492 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE;
493 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = cmd->c_dmamap->dm_nsegs;
494 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = cmd->c_dmamap->dm_segs;
  /src/sys/arch/arm/xscale/
pxa2x0_dmac.h 146 #define DMAC_DESC_SRC 0
pxa2x0_i2s.c 343 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
344 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = p->nsegs;
345 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = p->segs;
393 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
394 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
395 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
pxa2x0_dmac.c 144 #define ds_src_addr_hold ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_addr_hold
146 #define ds_src_burst ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_burst_size
148 #define ds_src_dma_segs ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_dma_segs
150 #define ds_src_nsegs ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_nsegs
837 src = &dxs->dxs_desc[DMAC_DESC_SRC];
842 if ((err = dmac_init_desc(&dxs->dxs_segs[DMAC_DESC_SRC], src, &size,
1042 src_ds = &dxs->dxs_segs[DMAC_DESC_SRC];
1044 src_xd = &dxs->dxs_desc[DMAC_DESC_SRC];
1257 if (dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs == 0 ||
pxa2x0_ac97.c 785 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
786 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;
787 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;
844 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
845 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
846 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
pxa2x0_mci.c 268 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
269 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
270 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr;
292 sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
640 dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC];

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