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Searched refs:DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h	`5927 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L`
dce_8_0_sh_mask.h	`8065 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100`
dce_10_0_sh_mask.h	`7121 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 [all...]`
dce_11_0_sh_mask.h	`7005 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 [all...]`
dce_11_2_sh_mask.h	`8109 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 [all...]`
dce_12_0_sh_mask.h	`5039 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_sh_mask.h	`4043 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L [all...]`
dcn_2_0_0_sh_mask.h	`2817 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L [all...]`
dcn_2_1_0_sh_mask.h	`2549 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L [all...]`

Completed in 949 milliseconds