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    Searched refs:DMUB_SR (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
dmub_dcn20.h 38 DMUB_SR(DMCUB_CNTL) \
39 DMUB_SR(DMCUB_MEM_CNTL) \
40 DMUB_SR(DMCUB_SEC_CNTL) \
41 DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
42 DMUB_SR(DMCUB_INBOX1_SIZE) \
43 DMUB_SR(DMCUB_INBOX1_RPTR) \
44 DMUB_SR(DMCUB_INBOX1_WPTR) \
45 DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
46 DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
47 DMUB_SR(DMCUB_REGION3_CW2_OFFSET)
    [all...]
amdgpu_dmub_dcn21.c 46 #define DMUB_SR(reg) REG_OFFSET(reg),
48 #undef DMUB_SR
amdgpu_dmub_dcn20.c 47 #define DMUB_SR(reg) REG_OFFSET(reg),
49 #undef DMUB_SR

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