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    Searched refs:DM_PP_MAX_CLOCK_LEVELS (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_services_types.h 97 #define DM_PP_MAX_CLOCK_LEVELS 16
101 uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
111 struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
121 struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_pp_smu.c 262 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
266 DM_PP_MAX_CLOCK_LEVELS);
268 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
292 DM_PP_MAX_CLOCK_LEVELS);
294 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
315 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
319 DM_PP_MAX_CLOCK_LEVELS);
321 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;

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