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    Searched refs:DOMAIN0_PG_STATUS (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_hwseq.h 199 SR(DOMAIN0_PG_STATUS), \
254 SR(DOMAIN0_PG_STATUS), \
312 SR(DOMAIN0_PG_STATUS), \
380 uint32_t DOMAIN0_PG_STATUS;
561 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
617 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
665 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 500 REG_WAIT(DOMAIN0_PG_STATUS,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 608 REG_WAIT(DOMAIN0_PG_STATUS,

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