| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_link_encoder.h | 55 SRI(DP_CONFIG, DP, id), \
56 SRI(DP_DPHY_CNTL, DP, id), \
57 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
58 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
59 SRI(DP_DPHY_SYM0, DP, id), \
60 SRI(DP_DPHY_SYM1, DP, id), \
61 SRI(DP_DPHY_SYM2, DP, id), \
62 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
63 SRI(DP_LINK_CNTL, DP, id), \
64 SRI(DP_LINK_FRAMING_CNTL, DP, id),
[all...] |
| dce_stream_encoder.h | 86 SRI(DP_MSE_RATE_CNTL, DP, id), \
87 SRI(DP_MSE_RATE_UPDATE, DP, id), \
88 SRI(DP_PIXEL_FORMAT, DP, id), \
89 SRI(DP_SEC_CNTL, DP, id), \
90 SRI(DP_STEER_FIFO, DP, id), \
91 SRI(DP_VID_M, DP, id), \
92 SRI(DP_VID_N, DP, id), \
93 SRI(DP_VID_STREAM_CNTL, DP, id), \
94 SRI(DP_VID_TIMING, DP, id), \
95 SRI(DP_SEC_AUD_N, DP, id),
[all...] |
| /src/sys/stand/ |
| ls.c | 84 typedef struct dirent DP;
89 register char *dp; local
94 for (dp = dirbuf; (dp < (dirbuf + size)) &&
95 (dp + ((DP *)dp)->d_reclen) < (dirbuf + size);
96 dp += ((DP *)dp)->d_reclen)
[all...] |
| /src/share/examples/rump/virtual_ip_router/ |
| rumprouter.c | 58 #define DP if (1) printf
60 #define DP if (0) printf
71 DP("Entering %s\n", __FUNCTION__);
73 DP("Create an interface(%s)\n", ifname);
79 DP("Get a socket for configuring the interface\n");
104 DP("Set the addresses\n");
110 DP("Done with %s\n", __FUNCTION__);
126 DP("Entering %s\n", __FUNCTION__);
128 DP("Open a routing socket\n");
168 DP("Set the route\n")
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_link_encoder.h | 48 SRI(DP_CONFIG, DP, id), \
49 SRI(DP_DPHY_CNTL, DP, id), \
50 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
51 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
52 SRI(DP_DPHY_SYM0, DP, id), \
53 SRI(DP_DPHY_SYM1, DP, id), \
54 SRI(DP_DPHY_SYM2, DP, id), \
55 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
56 SRI(DP_LINK_CNTL, DP, id), \
57 SRI(DP_LINK_FRAMING_CNTL, DP, id),
[all...] |
| dcn10_stream_encoder.h | 75 SRI(DP_DB_CNTL, DP, id), \
76 SRI(DP_MSA_MISC, DP, id), \
77 SRI(DP_MSA_COLORIMETRY, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
82 SRI(DP_MSE_RATE_CNTL, DP, id), \
83 SRI(DP_MSE_RATE_UPDATE, DP, id), \
84 SRI(DP_PIXEL_FORMAT, DP, id),
[all...] |
| amdgpu_dcn10_resource.c | 311 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1357 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_stream_encoder.h | 39 SRI(DP_DSC_CNTL, DP, id), \
40 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
42 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
44 SRI(DP_SEC_FRAMING4, DP, id)
|
| /src/sys/arch/x86/include/ |
| pmap.h | 84 #define pmap_copy(DP,SP,D,L,S) __USE(L)
87 #define pmap_move(DP,SP,D,L,S)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_sorgv100.c | 75 case 8: state->proto = DP; state->link = 1; break;
76 case 9: state->proto = DP; state->link = 2; break;
98 .dp = {
|
| nouveau_nvkm_engine_disp_sorgf119.c | 80 const u32 shift = sor->func->dp.lanes[ln] * 8;
112 clksor |= sor->dp.bw << 18;
113 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
114 if (sor->dp.mst)
116 if (sor->dp.ef)
153 case 8: state->proto = DP; state->link = 1; break;
154 case 9: state->proto = DP; state->link = 2; break;
171 .dp = {
|
| nouveau_nvkm_engine_disp_sorg94.c | 67 const u32 shift = sor->func->dp.lanes[ln] * 8;
97 mask |= 1 << sor->func->dp.lanes[i];
116 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
117 if (sor->dp.ef)
119 if (sor->dp.bw > 0x06)
254 case 8: state->proto = DP; state->link = 1; break;
255 case 9: state->proto = DP; state->link = 2; break;
272 .dp = {
|
| ior.h | 32 DP,
39 /* Armed DP state. */
45 } dp; member in struct:nvkm_ior
88 } dp; member in struct:nvkm_ior_func
|
| nouveau_nvkm_engine_disp_outp.c | 73 case DCB_OUTPUT_DP : *type = SOR; return DP;
|
| nouveau_nvkm_engine_disp_nv50.c | 334 const u32 linkKBps = ior->dp.bw * 27000;
346 h = h - (3 * ior->dp.ef) - (12 / ior->dp.nr);
352 v = v - ((36 / ior->dp.nr) + 3) - 1;
354 ior->func->dp.audio_sym(ior, head->id, h, v);
357 link_data_rate = (khz * head->asy.or.depth / 8) / ior->dp.nr;
363 for (TU = 64; ior->func->dp.activesym && TU >= 32; TU--) {
414 if (ior->func->dp.activesym) {
416 nvkm_error(subdev, "unable to determine dp config\n");
419 ior->func->dp.activesym(ior, head->id, bestTU
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp.c | 76 /* DP DSC throughput values used for slice count calculations KPixels/s */
81 /* DP DSC FEC Overhead factor = 1/(0.972261) */
132 /* Constants for DP DSC configurations */
142 * @intel_dp: DP struct
144 * If a CPU or PCH DP output is attached to an eDP panel, this function
576 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
603 * Older platforms don't like hdisplay==4096 with DP.
754 #define with_pps_lock(dp, wf) \
755 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))
6266 struct intel_dp *dp = &intel_dig_port->dp; local
6318 struct intel_dp *dp = &intel_dig_port->dp; local
[all...] |
| intel_dp_link_training.c | 171 intel_dp->DP |= DP_PORT_EN;
182 * The DP 1.4 spec defines the max clock recovery retries value
183 * as 10 but for pre-DP 1.4 devices we set a very tolerant
327 DRM_DEBUG_KMS("Channel EQ done. DP Training "
|
| intel_ddi.c | 78 * them for both DP and FDI transports, allowing those ports to
390 /* Voltage Swing Programming for VccIO 0.85V for DP */
431 /* Voltage Swing Programming for VccIO 0.95V for DP */
477 /* Voltage Swing Programming for VccIO 1.05V for DP */
711 /* Only DDIA and DDIE can select the 10th register with DP */
966 * DP/eDP/FDI use cases.
1250 intel_dp->DP = intel_dig_port->saved_port_bits |
1252 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1802 * As per DP 1.2 spec section 2.3.4.3 while sending
1810 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indicatio
[all...] |
| intel_display_types.h | 189 * encoder are flushed (for example for DP AUX transactions) and
245 * from HDCP over DP, so to account for these differences, we need to
249 * - DP AUX vs. DDC
250 * HDCP registers on the receiver are set via DP AUX for DP, and
253 * The offsets of the registers are different for DP vs. HDMI
256 * place on DP vs HDMI
258 * Seriously. In the DP spec, the 16-bit register containing
260 * BSTATUS. To confuse matters further, DP has a BSTATUS register
263 * On HDMI, the ksv fifo is read all at once, whereas on DP it mus
1344 struct intel_dp dp; member in struct:intel_digital_port
[all...] |
| /src/tests/net/if_ipsec/ |
| t_ipsec_pfil.sh | 93 unique=`$HIJACKING setkey -DP | grep -A2 "^${src}.*(${proto})$" | grep unique | sed 's/.*unique#//'`
124 $DEBUG && $HIJACKING setkey -DP
|
| t_ipsec_unnumbered.sh | 137 $DEBUG && $HIJACKING setkey -DP
150 $DEBUG && $HIJACKING setkey -DP
|
| t_ipsec.sh | 229 unique=`$HIJACKING setkey -DP | grep -A2 "^${src}.*(${proto})$" | grep unique | sed 's/.*unique#//'`
310 $DEBUG && $HIJACKING setkey -DP
480 $DEBUG && $HIJACKING setkey -DP
|
| t_ipsec_natt.sh | 421 $HIJACKING setkey -DP
|
| /src/tests/net/ipsec/ |
| t_ipsec_forwarding.sh | 92 $DEBUG && $HIJACKING setkey -DP
101 $DEBUG && $HIJACKING setkey -DP
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 264 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
|
