| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_link_encoder.h | 55 SRI(DP_CONFIG, DP, id), \
56 SRI(DP_DPHY_CNTL, DP, id), \
57 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
58 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
59 SRI(DP_DPHY_SYM0, DP, id), \
60 SRI(DP_DPHY_SYM1, DP, id), \
61 SRI(DP_DPHY_SYM2, DP, id), \
62 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
63 SRI(DP_LINK_CNTL, DP, id), \
64 SRI(DP_LINK_FRAMING_CNTL, DP, id),
[all...] |
| dce_stream_encoder.h | 86 SRI(DP_MSE_RATE_CNTL, DP, id), \
87 SRI(DP_MSE_RATE_UPDATE, DP, id), \
88 SRI(DP_PIXEL_FORMAT, DP, id), \
89 SRI(DP_SEC_CNTL, DP, id), \
90 SRI(DP_STEER_FIFO, DP, id), \
91 SRI(DP_VID_M, DP, id), \
92 SRI(DP_VID_N, DP, id), \
93 SRI(DP_VID_STREAM_CNTL, DP, id), \
94 SRI(DP_VID_TIMING, DP, id), \
95 SRI(DP_SEC_AUD_N, DP, id),
[all...] |
| /src/sys/stand/ |
| ls.c | 84 typedef struct dirent DP;
89 register char *dp; local in function:ls
94 for (dp = dirbuf; (dp < (dirbuf + size)) &&
95 (dp + ((DP *)dp)->d_reclen) < (dirbuf + size);
96 dp += ((DP *)dp)->d_reclen)
[all...] |
| /src/share/examples/rump/virtual_ip_router/ |
| rumprouter.c | 58 #define DP if (1) printf
60 #define DP if (0) printf
71 DP("Entering %s\n", __FUNCTION__);
73 DP("Create an interface(%s)\n", ifname);
79 DP("Get a socket for configuring the interface\n");
104 DP("Set the addresses\n");
110 DP("Done with %s\n", __FUNCTION__);
126 DP("Entering %s\n", __FUNCTION__);
128 DP("Open a routing socket\n");
168 DP("Set the route\n")
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_link_encoder.h | 48 SRI(DP_CONFIG, DP, id), \
49 SRI(DP_DPHY_CNTL, DP, id), \
50 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
51 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
52 SRI(DP_DPHY_SYM0, DP, id), \
53 SRI(DP_DPHY_SYM1, DP, id), \
54 SRI(DP_DPHY_SYM2, DP, id), \
55 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
56 SRI(DP_LINK_CNTL, DP, id), \
57 SRI(DP_LINK_FRAMING_CNTL, DP, id),
[all...] |
| dcn10_stream_encoder.h | 75 SRI(DP_DB_CNTL, DP, id), \
76 SRI(DP_MSA_MISC, DP, id), \
77 SRI(DP_MSA_COLORIMETRY, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
82 SRI(DP_MSE_RATE_CNTL, DP, id), \
83 SRI(DP_MSE_RATE_UPDATE, DP, id), \
84 SRI(DP_PIXEL_FORMAT, DP, id),
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_stream_encoder.h | 39 SRI(DP_DSC_CNTL, DP, id), \
40 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
42 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
44 SRI(DP_SEC_FRAMING4, DP, id)
|
| /src/sys/arch/x86/include/ |
| pmap.h | 84 #define pmap_copy(DP,SP,D,L,S) __USE(L)
87 #define pmap_move(DP,SP,D,L,S)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_sorgv100.c | 75 case 8: state->proto = DP; state->link = 1; break;
76 case 9: state->proto = DP; state->link = 2; break;
98 .dp = {
|
| nouveau_nvkm_engine_disp_sorgf119.c | 80 const u32 shift = sor->func->dp.lanes[ln] * 8;
112 clksor |= sor->dp.bw << 18;
113 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
114 if (sor->dp.mst)
116 if (sor->dp.ef)
153 case 8: state->proto = DP; state->link = 1; break;
154 case 9: state->proto = DP; state->link = 2; break;
171 .dp = {
|
| nouveau_nvkm_engine_disp_sorg94.c | 67 const u32 shift = sor->func->dp.lanes[ln] * 8;
97 mask |= 1 << sor->func->dp.lanes[i];
116 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
117 if (sor->dp.ef)
119 if (sor->dp.bw > 0x06)
254 case 8: state->proto = DP; state->link = 1; break;
255 case 9: state->proto = DP; state->link = 2; break;
272 .dp = {
|
| ior.h | 32 DP,
39 /* Armed DP state. */
45 } dp; member in struct:nvkm_ior
88 } dp; member in struct:nvkm_ior_func
|
| nouveau_nvkm_engine_disp_outp.c | 73 case DCB_OUTPUT_DP : *type = SOR; return DP;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp.c | 76 /* DP DSC throughput values used for slice count calculations KPixels/s */
81 /* DP DSC FEC Overhead factor = 1/(0.972261) */
132 /* Constants for DP DSC configurations */
142 * @intel_dp: DP struct
144 * If a CPU or PCH DP output is attached to an eDP panel, this function
576 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
603 * Older platforms don't like hdisplay==4096 with DP.
754 #define with_pps_lock(dp, wf) \
755 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))
6266 struct intel_dp *dp = &intel_dig_port->dp; local in function:intel_dp_hdcp2_wait_for_msg
6318 struct intel_dp *dp = &intel_dig_port->dp; local in function:intel_dp_hdcp2_write_msg
[all...] |
| intel_dp_link_training.c | 171 intel_dp->DP |= DP_PORT_EN;
182 * The DP 1.4 spec defines the max clock recovery retries value
183 * as 10 but for pre-DP 1.4 devices we set a very tolerant
327 DRM_DEBUG_KMS("Channel EQ done. DP Training "
|
| /src/tests/net/if_ipsec/ |
| t_ipsec_pfil.sh | 93 unique=`$HIJACKING setkey -DP | grep -A2 "^${src}.*(${proto})$" | grep unique | sed 's/.*unique#//'`
124 $DEBUG && $HIJACKING setkey -DP
|
| t_ipsec_unnumbered.sh | 137 $DEBUG && $HIJACKING setkey -DP
150 $DEBUG && $HIJACKING setkey -DP
|
| t_ipsec.sh | 229 unique=`$HIJACKING setkey -DP | grep -A2 "^${src}.*(${proto})$" | grep unique | sed 's/.*unique#//'`
310 $DEBUG && $HIJACKING setkey -DP
480 $DEBUG && $HIJACKING setkey -DP
|
| t_ipsec_natt.sh | 421 $HIJACKING setkey -DP
|
| /src/libexec/ld.aout_so/ |
| ld.so.sparc.uue | 129 MH``"@``(^`0@'-`$8!"6$"`!D`2`"-0%X,1``#PCDA``"("DP!HZ@`"ET`8@
144 M$"``I@3@#("DP!H*O_]BK`6@#-`&(!2`HB``%H``%P$```#0!@``@*(@`!*`
430 M[O8DP`#0!>&LX"3@!-`DP`#2![_PI@3@"-`'O^R2`D`0D`(@`=(GO_"`HB`'
432 M![ZKE!`@`=`DP`#4).`$T@>_\*8$X`C0![_L$(``#Y("8`&`C2`"`H``%Y`0
438 M!-`DP`#2![_PI@3@"-`'O^R2`D`0D`(@`=(GO_"`HB`'!(``"-`GO^R0$``=
442 M[O8DP`#0!>&PX"3@!-`DP`#2![_PI@3@"-`'O^R2`D`0D`(@`=(GO_"`HB`'
448 M!>&LX"3@!-`DP`#2![_PU`>_[)("0!"4`J`!TB>_\("BH`<$@``(U">_[)`0
645 M`!#6!>(HD!``$T``)D"4$"`$F2P@`L`DP`S0!,``@*(@``*``!FH$"``HA``
702 MF+*&?_\"@``=I@8`&H"DP!@(@``7HA``$Z0D0!J0$``2G\;``)(0`!&`HB``
1048 M(H``E@+@!!*___J4`J`$$(``#:8DP!J6$``0E!``$](*P`"8@S__T`J``-`
[all...] |
| ld.so.arm.uue | 789 MH.$.,)3E!+!,XB,XL.$$```:Z2,`ZPDPH.,`,(#E``#@XS"H&^DP$)3E`""@
860 M@`OE"$":YP``E.4``%#C&R``&P!0A.4`8(?E5#R6Y0``D^4``%#C`0``"DP@
930 MXP@```I8<$OB@!"7Z`PP9^`$`%/A$@``.DP`&^5<$!OE!""@X78=`.L`,)7E
1029 M&^4$P&?B#`"@X0'`7.(+``!*7)`;Y0`0H..,(*#A`3""X@DP@^`)((+@`!#"
1256 M$0$`KP``)!@1`0`````DP!0!`%,``$30%`$`N0``1!P1`0`````D(!$!````
1263 M````)'01`0`````D>!$!`````"1\$0$`````)(`1`0`````DP!4!`"\``$30
1268 M```DP!$!`#D``"3$$0$`````)%`6`0`M``!$R!$!`````"3,$0$`.P``)-`1
1289 M`"2L$@$`````)+`2`0`````DM!(!`````"2X$@$`````)+P2`0`````DP!(!
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| sdm845-cheza.dtsi | 769 * - The only source of DP is the single native Type C port.
770 * - On cheza we want to be able to hook DP up to _either_ of the
771 * two Type C connectors and want to be able to achieve 4 lanes of DP.
772 * - When you configure a Type C port for 4 lanes of DP you lose USB3.
774 * configured as 4-lanes DP so it's always available.
793 * We always need the high speed pins as 4-lanes DP in case someone
794 * hotplugs a DP peripheral. Thus limit this port to a max of high
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/xilinx/ |
| zynqmp-zcu102-revA.dts | 223 output-low; /* PCIE = 0, DP = 1 */
229 output-high; /* PCIE = 0, DP = 1 */
510 /* refclk0 for PS-GT, used for DP */
651 /* pcie, sata, usb3, dp */
706 phy-names = "dp-phy0";
|
| /src/tests/net/ipsec/ |
| t_ipsec_forwarding.sh | 92 $DEBUG && $HIJACKING setkey -DP
101 $DEBUG && $HIJACKING setkey -DP
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/ |
| tegra186-p3509-0000+p3636-0001.dts | 320 /* DP */
324 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
325 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
334 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
335 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
|
