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Searched refs:DPCLKA_CFGCR0 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_ddi.c	`2983 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 3122 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. / 3123 val = I915_READ(DPCLKA_CFGCR0); 3126 I915_WRITE(DPCLKA_CFGCR0, val); 3129 Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3133 val = I915_READ(DPCLKA_CFGCR0); 3135 I915_WRITE(DPCLKA_CFGCR0, val); 3165 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) \|`
intel_display.c	`10581 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);`
/src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h	`10023 #define DPCLKA_CFGCR0 _MMIO(0x6C200)`

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