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    Searched refs:DPG_PIPE_NB_PSTATE_CHANGE_CONTROL (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_mem_input.h 65 SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
112 uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
191 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
192 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
193 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
194 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
amdgpu_dce_mem_input.c 206 if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {
210 REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
215 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,

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