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    Searched refs:DPLL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
xlnx-zynqmp-clk.h 17 #define DPLL 3
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dvo.c 452 u32 dpll[I915_MAX_PIPES]; local in function:intel_dvo_init
489 dpll[pipe] = I915_READ(DPLL(pipe));
490 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
497 I915_WRITE(DPLL(pipe), dpll[pipe]);
intel_display.c 580 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
592 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
594 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
597 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
609 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
621 int chv_calc_dpll_params(int refclk, struct dpll *clock)
642 const struct dpll *clock)
715 int target, int refclk, struct dpll *match_clock
1511 u32 dpll = crtc_state->dpll_hw_state.dpll; local in function:i9xx_enable_pll
8480 u32 dpll; local in function:i9xx_compute_dpll
8554 u32 dpll; local in function:i8xx_compute_dpll
10025 u32 dpll, fp, fp2; local in function:ilk_compute_dpll
11878 u32 dpll = pipe_config->dpll_hw_state.dpll; local in function:i9xx_pll_refclk
11897 u32 dpll = pipe_config->dpll_hw_state.dpll; local in function:i9xx_crtc_clock_get
17703 u32 dpll, fp; local in function:i830_enable_pipe
    [all...]
intel_display_power.c 1271 * CHV DPLL B/C have some issues if VGA mode is enabled.
1274 u32 val = I915_READ(DPLL(pipe));
1280 I915_WRITE(DPLL(pipe), val);
1438 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1616 * (eg. for pipe B DPLL) the entire channel will
5088 u32 status = I915_READ(DPLL(PIPE_A));
5161 /* cmnlane needs DPLL registers */
intel_dp.c 92 struct dpll dpll; member in struct:dp_link_dpll
791 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
794 * The DPLL for the pipe must be enabled for this to work.
802 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
1816 pipe_config->dpll = divisor[i].dpll;
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
exynos5422-odroid-core.dtsi 97 /* derived from 600MHz DPLL */
199 /* derived from 600MHz DPLL */
235 /* derived from 600MHz DPLL */
247 /* derived from 600MHz DPLL */
262 /* derived from 600MHz DPLL */
rk3036.dtsi 237 * Fix the emac parent clock is DPLL instead of APLL.
  /src/sys/arch/arm/samsung/
exynos_soc.c 432 DUMP_PLL(5, DPLL);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 3363 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3446 * Selects the phase for the 10X DPLL clock for the PCIe
3478 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3484 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
4754 * the DPLL semantics change when the LVDS is assigned to that pipe.
4795 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
9961 /* DPLL control1 */
9976 /* DPLL control2 */
9984 /* DPLL Status */
9988 /* DPLL cfg *
    [all...]

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