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    Searched refs:DPP (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNHazardRecognizer.h 76 int checkDPPHazards(MachineInstr *DPP);
AMDGPUAtomicOptimizer.cpp 150 // we have DPP available on our subtarget, and the atomic operation is 32
224 // we have DPP available on our subtarget, and the atomic operation is 32
299 {Identity, V, B.getInt32(DPP::ROW_XMASK0 | 1 << Idx),
336 {Identity, V, B.getInt32(DPP::ROW_SHR0 | 1 << Idx),
340 // GFX9 has DPP row broadcast operations.
344 {Identity, V, B.getInt32(DPP::BCAST15), B.getInt32(0xa),
349 {Identity, V, B.getInt32(DPP::BCAST31), B.getInt32(0xc),
352 // On GFX10 all DPP operations are confined to a single row. To get cross-
364 {Identity, PermX, B.getInt32(DPP::QUAD_PERM_ID),
373 {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID)
    [all...]
SIDefines.h 42 DPP = 1 << 15,
250 DPP = 4
672 namespace DPP {
728 } // namespace DPP
SIInstrInfo.h 607 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
611 return get(Opcode).TSFlags & SIInstrFlags::DPP;
GCNHazardRecognizer.cpp 638 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) {
642 // Check for DPP VGPR read after VALU VGPR write and EXEC write.
650 for (const MachineOperand &Use : DPP->uses()) {
SIInstrInfo.cpp 4255 using namespace AMDGPU::DPP;
4309 "64 bit dpp only support row_newbcast";
7507 // to be selected by dpp combiner or sdwa peepholer.
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.h 895 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUInstPrinter.cpp 374 } else if (Flags & SIInstrFlags::DPP) {
807 using namespace AMDGPU::DPP;
817 O << " /* 64 bit dpp only supports row_newbcast */";
928 using namespace llvm::AMDGPU::DPP;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1903 // GFX90A allows DPP on 64-bit operands.
3058 (isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) ||
3084 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, AMDGPUAsmVariants::DPP
3109 static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};
3127 return "dpp";
3961 Error(S, "64 bit dpp only supports row_newbcast");
7641 // dpp
7649 using namespace AMDGPU::DPP;
7751 // dpp
7848 using namespace AMDGPU::DPP;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 402 // not parse a dpp if the correct literal is not set. For dpp16 the
403 // autogenerated decoder checks the dpp literal
405 using namespace llvm::AMDGPU::DPP;
429 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
  /src/external/bsd/wpa/dist/src/drivers/
driver_nl80211.c 2579 /* DPP Public Action */
3362 __AKM(DPP, DPP);
13847 "nl80211: Update DPP Public Action frame registration (%s multicast RX)",

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