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    Searched refs:DPP_TOP0_DPP_CRC_VAL_R_G (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_hwseq.h 231 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
296 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
409 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 127 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
128 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));

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