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    Searched refs:DP_MSE_SAT_UPDATE (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_link_encoder.h 68 SRI(DP_MSE_SAT_UPDATE, DP, id), \
149 uint32_t DP_MSE_SAT_UPDATE;
amdgpu_dce_link_encoder.c 1317 /* DP_MSE_SAT_UPDATE:
1322 REG_UPDATE(DP_MSE_SAT_UPDATE,
1323 DP_MSE_SAT_UPDATE, 1);
1326 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1338 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1340 REG_GET(DP_MSE_SAT_UPDATE,
1341 DP_MSE_SAT_UPDATE, &value1);
1343 REG_GET(DP_MSE_SAT_UPDATE,
1346 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_link_encoder.h 61 SRI(DP_MSE_SAT_UPDATE, DP, id), \
101 uint32_t DP_MSE_SAT_UPDATE;
206 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
255 type DP_MSE_SAT_UPDATE;\
amdgpu_dcn10_link_encoder.c 1284 /* DP_MSE_SAT_UPDATE:
1289 REG_UPDATE(DP_MSE_SAT_UPDATE,
1290 DP_MSE_SAT_UPDATE, 1);
1293 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1305 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1307 REG_GET(DP_MSE_SAT_UPDATE,
1308 DP_MSE_SAT_UPDATE, &value1);
1310 REG_GET(DP_MSE_SAT_UPDATE,
1313 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */

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