HomeSort by: relevance | last modified time | path
    Searched refs:DP_SEC_STREAM_ENABLE (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 756 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
850 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
870 DP_SEC_STREAM_ENABLE, 0);
877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1454 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1469 DP_SEC_STREAM_ENABLE, 0);
1476 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
dcn10_stream_encoder.h 206 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
390 type DP_SEC_STREAM_ENABLE;\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c 338 DP_SEC_STREAM_ENABLE, 1);
364 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
439 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 896 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
914 DP_SEC_STREAM_ENABLE, 0);
922 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1518 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1533 DP_SEC_STREAM_ENABLE, 0);
1539 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
dce_stream_encoder.h 157 SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
240 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
431 uint8_t DP_SEC_STREAM_ENABLE;
562 uint32_t DP_SEC_STREAM_ENABLE;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v6_0.c 1642 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

Completed in 19 milliseconds