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    Searched refs:DP_SEC_TIMESTAMP_MODE (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 199 SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
279 SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
475 uint8_t DP_SEC_TIMESTAMP_MODE;
606 uint32_t DP_SEC_TIMESTAMP_MODE;
amdgpu_dce_stream_encoder.c 1460 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 249 SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
439 type DP_SEC_TIMESTAMP_MODE;\
amdgpu_dcn10_stream_encoder.c 1395 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_enum.h 2736 typedef enum DP_SEC_TIMESTAMP_MODE {
2739 } DP_SEC_TIMESTAMP_MODE;
dce_11_2_enum.h 3173 typedef enum DP_SEC_TIMESTAMP_MODE {
3176 } DP_SEC_TIMESTAMP_MODE;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v6_0.c 1635 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 6050 * DP_SEC_TIMESTAMP_MODE enum
6053 typedef enum DP_SEC_TIMESTAMP_MODE {
6056 } DP_SEC_TIMESTAMP_MODE;
vega10_enum.h 8486 * DP_SEC_TIMESTAMP_MODE enum
8489 typedef enum DP_SEC_TIMESTAMP_MODE {
8492 } DP_SEC_TIMESTAMP_MODE;

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