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Searched refs:DP_STEER_FIFO_RESET (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c	`511 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); 514 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h	`166 SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ 248 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ 444 uint8_t DP_STEER_FIFO_RESET; 575 uint32_t DP_STEER_FIFO_RESET;`
amdgpu_dce_stream_encoder.c	`965 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 970 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 1018 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c	`922 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 927 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 982 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);`
dcn10_stream_encoder.h	`218 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ 408 type DP_STEER_FIFO_RESET;\`

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