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    Searched refs:DP_TP_CTL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_ddi.c 1156 /* Configure DP_TP_CTL with auto-training */
1157 I915_WRITE(DP_TP_CTL(PORT_E),
1219 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1220 temp = I915_READ(DP_TP_CTL(PORT_E));
1223 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1224 POSTING_READ(DP_TP_CTL(PORT_E));
1237 I915_WRITE(DP_TP_CTL(PORT_E),
3282 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3284 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3302 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4202 u32 dp_tp_ctl, ddi_buf_ctl; local
4342 i915_reg_t dp_tp_ctl; local
    [all...]
intel_dp.c 2522 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3481 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3507 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
4208 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4211 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
handlers.c 576 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
695 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
2476 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2477 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2478 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2479 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2480 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 9730 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)

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