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    Searched refs:DP_VID_M_N_GEN_EN (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c 481 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
492 DP_VID_M_N_GEN_EN, 1,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 167 SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
249 SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
445 uint8_t DP_VID_M_N_GEN_EN;
576 uint32_t DP_VID_M_N_GEN_EN;
amdgpu_dce_stream_encoder.c 999 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
1009 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 961 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
972 DP_VID_M_N_GEN_EN, 1,
dcn10_stream_encoder.h 219 SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
409 type DP_VID_M_N_GEN_EN;\
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_enum.h 2628 typedef enum DP_VID_M_N_GEN_EN {
2631 } DP_VID_M_N_GEN_EN;
dce_11_2_enum.h 3060 typedef enum DP_VID_M_N_GEN_EN {
3063 } DP_VID_M_N_GEN_EN;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 5782 * DP_VID_M_N_GEN_EN enum
5785 typedef enum DP_VID_M_N_GEN_EN {
5788 } DP_VID_M_N_GEN_EN;
vega10_enum.h 8202 * DP_VID_M_N_GEN_EN enum
8205 typedef enum DP_VID_M_N_GEN_EN {
8208 } DP_VID_M_N_GEN_EN;

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