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    Searched refs:DP_VID_N_MUL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 371 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
499 uint8_t DP_VID_N_MUL;
630 uint32_t DP_VID_N_MUL;
amdgpu_dce_stream_encoder.c 339 if (enc110->se_mask->DP_VID_N_MUL)
340 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c 493 DP_VID_N_MUL, n_multiply);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 302 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
464 type DP_VID_N_MUL;\
amdgpu_dcn10_stream_encoder.c 973 DP_VID_N_MUL, n_multiply);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 5791 * DP_VID_N_MUL enum
5794 typedef enum DP_VID_N_MUL {
5799 } DP_VID_N_MUL;

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