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    Searched refs:DP_VID_STREAM_DIS_DEFER (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 163 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
245 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
441 uint8_t DP_VID_STREAM_DIS_DEFER;
572 uint32_t DP_VID_STREAM_DIS_DEFER;
amdgpu_dce_stream_encoder.c 945 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
1027 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 215 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
405 type DP_VID_STREAM_DIS_DEFER;\
amdgpu_dcn10_stream_encoder.c 902 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
991 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_enum.h 2603 typedef enum DP_VID_STREAM_DIS_DEFER {
2607 } DP_VID_STREAM_DIS_DEFER;
dce_11_2_enum.h 3035 typedef enum DP_VID_STREAM_DIS_DEFER {
3039 } DP_VID_STREAM_DIS_DEFER;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 5736 * DP_VID_STREAM_DIS_DEFER enum
5739 typedef enum DP_VID_STREAM_DIS_DEFER {
5743 } DP_VID_STREAM_DIS_DEFER;
vega10_enum.h 8129 * DP_VID_STREAM_DIS_DEFER enum
8132 typedef enum DP_VID_STREAM_DIS_DEFER {
8136 } DP_VID_STREAM_DIS_DEFER;

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