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    Searched refs:DP_VID_TIMING (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c 481 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
491 REG_UPDATE_2(DP_VID_TIMING,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 336 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
340 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
999 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
1009 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
dce_stream_encoder.h 94 SRI(DP_VID_TIMING, DP, id), \
167 SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
318 SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
668 uint32_t DP_VID_TIMING;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 961 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
971 REG_UPDATE_2(DP_VID_TIMING,
dcn10_stream_encoder.h 92 SRI(DP_VID_TIMING, DP, id), \
137 uint32_t DP_VID_TIMING;

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