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    Searched refs:DRC (Results 1 - 8 of 8) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/sim/m32c/
reg.c 647 #define DRC(f, n, id) \
655 DRC (r[0].r_r0, "r0", r0);
656 DRC (r[0].r_r1, "r1", r1);
657 DRC (r[0].r_r2, "r2", r2);
658 DRC (r[0].r_r3, "r3", r3);
659 DRC (r[0].r_a0, "a0", a0);
660 DRC (r[0].r_a1, "a1", a1);
661 DRC (r[0].r_sb, "sb", sb);
662 DRC (r[0].r_fb, "fb", fb);
664 DRC (r[1].r_r0, "r0'", r0)
    [all...]
  /src/external/gpl3/gdb/dist/sim/m32c/
reg.c 647 #define DRC(f, n, id) \
655 DRC (r[0].r_r0, "r0", r0);
656 DRC (r[0].r_r1, "r1", r1);
657 DRC (r[0].r_r2, "r2", r2);
658 DRC (r[0].r_r3, "r3", r3);
659 DRC (r[0].r_a0, "a0", a0);
660 DRC (r[0].r_a1, "a1", a1);
661 DRC (r[0].r_sb, "sb", sb);
662 DRC (r[0].r_fb, "fb", fb);
664 DRC (r[1].r_r0, "r0'", r0)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonEarlyIfConv.cpp 203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC,
781 switch (DRC->getID()) {
802 Register MuxR = MRI->createVirtualRegister(DRC);
HexagonBitSimplify.cpp 933 auto *DRC = getFinalVRegClass(RD, MRI);
934 if (!DRC)
937 return DRC == getFinalVRegClass(RS, MRI);
1484 const BitTracker::RegisterCell &DRC = BT.lookup(DR);
1485 if (HBS::getConst(DRC, 0, DRC.width(), U)) {
1492 BT.put(ImmReg, DRC);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineVerifier.cpp 1898 if (const TargetRegisterClass *DRC =
1900 if (!DRC->contains(Reg)) {
1903 << TRI->getRegClassName(DRC) << " register.\n";
2007 if (const TargetRegisterClass *DRC =
2016 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2017 if (!DRC) {
2022 if (!RC->hasSuperClassEq(DRC)) {
2024 errs() << "Expected a " << TRI->getRegClassName(DRC)
MachineSink.cpp 279 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
280 if (SRC != DRC)
  /src/sys/arch/macppc/dev/
snapper.c 597 u_char DRC[6];
1776 { 1, 0, 0, 0, 0, 0 }, /* DRC */
1807 sizeof tas3004_initdata.DRC, /* 0x02 */
2048 DEQ_WRITE(sc, DEQ_DRC, tas3004_initdata.DRC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 4598 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
4600 return DRC->contains(Reg);
4610 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
4611 if (!DRC)
4614 return RC->hasSuperClassEq(DRC);

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