| /src/external/bsd/byacc/dist/test/btyacc/ |
| btyacc_calc1.tab.h | 6 #define DREG 257
|
| calc1.tab.h | 6 #define DREG 257
|
| varsyntax_calc1.tab.h | 6 #define DREG 257
18 int ival; /* dreg & vreg array index values*/
|
| /src/external/bsd/byacc/dist/test/yacc/ |
| calc1.tab.h | 3 #define DREG 257
|
| varsyntax_calc1.tab.h | 3 #define DREG 257
15 int ival; /* dreg & vreg array index values*/
|
| /src/external/gpl3/binutils/dist/gas/ |
| itbl-parse.h | 57 DREG = 258, /* DREG */
75 #define DREG 258
|
| itbl-parse.y | 129 type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
130 ; 'dreg', 'creg' or 'greg' specifies a data, control, or general
165 p1 dreg d1 1 ; data register "d1" for COP1 has value 1
183 p3 dreg d3 3 ; data register "d3" for COP3 has value 3
185 p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
197 COPz CO fun dreg creg immed
207 p3 dreg d3 3 ; data register "d3" for COP3 has value 3
209 p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
219 COPz CO fun dreg creg
242 to recognize 'dreg' etc. in context sensitive way
[all...] |
| itbl-lex.l | 48 "dreg"|"DREG" {
49 return DREG;
|
| /src/external/gpl3/binutils.old/dist/gas/ |
| itbl-parse.h | 57 DREG = 258, /* DREG */
75 #define DREG 258
|
| itbl-parse.y | 129 type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
130 ; 'dreg', 'creg' or 'greg' specifies a data, control, or general
165 p1 dreg d1 1 ; data register "d1" for COP1 has value 1
183 p3 dreg d3 3 ; data register "d3" for COP3 has value 3
185 p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
197 COPz CO fun dreg creg immed
207 p3 dreg d3 3 ; data register "d3" for COP3 has value 3
209 p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
219 COPz CO fun dreg creg
242 to recognize 'dreg' etc. in context sensitive way
[all...] |
| itbl-lex.l | 48 "dreg"|"DREG" {
49 return DREG;
|
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| bfin-sim.c | 383 case 0: case 1: return &DREG (reg);
497 if (p >= &DREG (0) && p <= &CYCLESREG)
498 return greg_names[p - &DREG (0)];
1161 /* DIVS ( Dreg, Dreg ) ;
1180 /* DIVQ ( Dreg, Dreg ) ;
1206 /* ONES ( Dreg ) ;
1342 bu32 s0 = DREG (src0), s1 = DREG (src1)
4701 bu32 v, dreg, sat = 0; local
4748 STORE (DREG (dst0), REG_H_L (DREG (dst0), dreg >> 16)); local
4753 STORE (DREG (dst0), dreg); local
4756 STORE (ASTATREG (az), dreg == 0); local
[all...] |
| interp.c | 119 sc.arg1 = args[0] = DREG (0);
120 sc.arg2 = args[1] = DREG (1);
121 sc.arg3 = args[2] = DREG (2);
122 sc.arg4 = args[3] = DREG (3);
123 sc.arg5 = args[4] = DREG (4);
124 sc.arg6 = args[5] = DREG (5);
130 sc.arg1 = args[0] = GET_LONG (DREG (0));
131 sc.arg2 = args[1] = GET_LONG (DREG (0) + 4);
132 sc.arg3 = args[2] = GET_LONG (DREG (0) + 8);
133 sc.arg4 = args[3] = GET_LONG (DREG (0) + 12)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| bfin-sim.c | 383 case 0: case 1: return &DREG (reg);
497 if (p >= &DREG (0) && p <= &CYCLESREG)
498 return greg_names[p - &DREG (0)];
1161 /* DIVS ( Dreg, Dreg ) ;
1180 /* DIVQ ( Dreg, Dreg ) ;
1206 /* ONES ( Dreg ) ;
1342 bu32 s0 = DREG (src0), s1 = DREG (src1)
4701 bu32 v, dreg, sat = 0; local
4748 STORE (DREG (dst0), REG_H_L (DREG (dst0), dreg >> 16)); local
4753 STORE (DREG (dst0), dreg); local
4756 STORE (ASTATREG (az), dreg == 0); local
[all...] |
| interp.c | 119 sc.arg1 = args[0] = DREG (0);
120 sc.arg2 = args[1] = DREG (1);
121 sc.arg3 = args[2] = DREG (2);
122 sc.arg4 = args[3] = DREG (3);
123 sc.arg5 = args[4] = DREG (4);
124 sc.arg6 = args[5] = DREG (5);
130 sc.arg1 = args[0] = GET_LONG (DREG (0));
131 sc.arg2 = args[1] = GET_LONG (DREG (0) + 4);
132 sc.arg3 = args[2] = GET_LONG (DREG (0) + 8);
133 sc.arg4 = args[3] = GET_LONG (DREG (0) + 12)
[all...] |
| /src/sys/arch/cobalt/stand/boot/ |
| lcd.c | 37 #define DREG 0x10
110 CSR_WRITE(lcd_base, DREG, message->row1[i]);
114 CSR_WRITE(lcd_base, DREG, message->row2[i]);
|
| /src/external/bsd/byacc/dist/test/ |
| btyacc_calc1.y | 24 double dreg[26];
38 %token <ival> DREG VREG /* indices into dreg, vreg arrays */
68 | DREG '=' dexp
70 dreg[$1] = $3;
79 | DREG
81 $$ = dreg[$1];
222 return (DREG);
|
| calc1.y | 26 double dreg[26];
40 %token <ival> DREG VREG /* indices into dreg, vreg arrays */
66 | DREG '=' dexp '\n'
68 dreg[$1] = $3;
81 | DREG
83 $$ = dreg[$1];
207 return (DREG);
|
| varsyntax_calc1.y | 27 double dreg[26];
36 int ival; // dreg & vreg array index values
41 %token <ival> DREG VREG // indices into dreg, vreg arrays */
68 | DREG '=' dexp '\n'
70 dreg[$1] = $3;
83 | DREG
85 $<dval>$ = dreg[$<ival>1]; // $$ & $1 are sufficient here
209 return (DREG);
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| rx-parse.y | 145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
931 | DCMP DREG ',' DREG { rx_check_dfpu();
948 | DMOV DOT_D DREG ',' DREG
951 | DMOV DOT_D DREG ',' '[' REG ']'
954 | DMOV DOT_D DREG ',' disp '[' REG ']'
958 | DMOV DOT_D '[' REG ']' ',' DREG
961 | DMOV DOT_D disp '[' REG ']' ',' DREG
[all...] |
| rx-parse.h | 61 DREG = 262, /* DREG */
230 #define DREG 262
|
| m68k-parse.h | 306 DREG,
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| rx-parse.y | 145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
931 | DCMP DREG ',' DREG { rx_check_dfpu();
948 | DMOV DOT_D DREG ',' DREG
951 | DMOV DOT_D DREG ',' '[' REG ']'
954 | DMOV DOT_D DREG ',' disp '[' REG ']'
958 | DMOV DOT_D '[' REG ']' ',' DREG
961 | DMOV DOT_D disp '[' REG ']' ',' DREG
[all...] |
| rx-parse.h | 61 DREG = 262, /* DREG */
230 #define DREG 262
|
| /src/sys/dev/ic/ |
| mb89352reg.h | 69 #define DREG 0x0a /* Data Register (R/W) */
|
