| /src/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| logger_types.h | 37 #define DC_LOG_DEBUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
38 #define DC_LOG_DC(...) DRM_DEBUG_KMS(__VA_ARGS__)
39 #define DC_LOG_DTN(...) DRM_DEBUG_KMS(__VA_ARGS__)
41 #define DC_LOG_HW_HOTPLUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
43 #define DC_LOG_HW_SET_MODE(...) DRM_DEBUG_KMS(__VA_ARGS__)
44 #define DC_LOG_HW_RESUME_S3(...) DRM_DEBUG_KMS(__VA_ARGS__)
46 #define DC_LOG_HW_HPD_IRQ(...) DRM_DEBUG_KMS(__VA_ARGS__)
47 #define DC_LOG_MST(...) DRM_DEBUG_KMS(__VA_ARGS__)
51 #define DC_LOG_BANDWIDTH_VALIDATION(...) DRM_DEBUG_KMS(__VA_ARGS__)
52 #define DC_LOG_I2C_AUX(...) DRM_DEBUG_KMS(__VA_ARGS__
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| dvo_tfp410.c | 130 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
155 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
190 DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
197 DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
276 DRM_DEBUG_KMS("TFP410_REV: 0x%02X\n", val);
278 DRM_DEBUG_KMS("TFP410_CTL1: 0x%02X\n", val);
280 DRM_DEBUG_KMS("TFP410_CTL2: 0x%02X\n", val);
282 DRM_DEBUG_KMS("TFP410_CTL3: 0x%02X\n", val);
284 DRM_DEBUG_KMS("TFP410_USERCFG: 0x%02X\n", val);
286 DRM_DEBUG_KMS("TFP410_DE_DLY: 0x%02X\n", val)
[all...] |
| dvo_ivch.c | 232 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
260 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
292 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
339 DRM_DEBUG_KMS("Resetting the IVCH registers\n");
450 DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
452 DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
454 DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
456 DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
458 DRM_DEBUG_KMS("VR40: 0x%04x\n", val);
462 DRM_DEBUG_KMS("VR80: 0x%04x\n", val)
[all...] |
| intel_dp_link_training.c | 37 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
151 DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
153 DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
206 DRM_DEBUG_KMS("clock recovery OK\n");
211 DRM_DEBUG_KMS("Same voltage tried 5 times\n");
216 DRM_DEBUG_KMS("Max Voltage Swing reached\n");
264 DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
266 DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
279 DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
281 DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n")
[all...] |
| intel_lspcon.c | 96 DRM_DEBUG_KMS("Vendor: Mega Chips\n");
101 DRM_DEBUG_KMS("Vendor: Parade Tech\n");
118 DRM_DEBUG_KMS("Error reading LSPCON mode\n");
133 DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n",
141 DRM_DEBUG_KMS("Current LSPCON mode %s\n",
161 DRM_DEBUG_KMS("Current mode = desired LSPCON mode\n");
172 DRM_DEBUG_KMS("LSPCON mode changed done\n");
182 DRM_DEBUG_KMS("Native AUX CH down\n");
186 DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n",
228 DRM_DEBUG_KMS("No LSPCON detected, found %s\n"
[all...] |
| intel_dp_aux_backlight.c | 43 DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
54 DRM_DEBUG_KMS("Failed to %s aux backlight\n",
71 DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
102 DRM_DEBUG_KMS("Failed to write aux backlight level\n");
127 DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
129 DRM_DEBUG_KMS("Use panel default backlight frequency\n");
144 DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
149 DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
158 DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
171 DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n")
[all...] |
| dvo_sil164.c | 105 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
130 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
157 DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
166 DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
172 DRM_DEBUG_KMS("init sil164 dvo controller successfully!\n");
255 DRM_DEBUG_KMS("SIL164_FREQ_LO: 0x%02x\n", val);
257 DRM_DEBUG_KMS("SIL164_FREQ_HI: 0x%02x\n", val);
259 DRM_DEBUG_KMS("SIL164_REG8: 0x%02x\n", val);
261 DRM_DEBUG_KMS("SIL164_REG9: 0x%02x\n", val);
263 DRM_DEBUG_KMS("SIL164_REGC: 0x%02x\n", val)
[all...] |
| intel_bios.c | 239 DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type);
242 DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n",
247 DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type);
262 DRM_DEBUG_KMS("DRRS supported mode is static\n");
266 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
270 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
307 DRM_DEBUG_KMS("Found panel mode in BIOS VBT legacy lfp table:\n");
318 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
394 DRM_DEBUG_KMS("Found panel mode in BIOS VBT generic dtd table:\n");
431 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n"
[all...] |
| intel_dsi_vbt.c | 144 DRM_DEBUG_KMS("\n");
166 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
222 DRM_DEBUG_KMS("\n");
239 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
252 DRM_DEBUG_KMS("SC gpio not supported\n");
255 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
299 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
304 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
354 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
364 DRM_DEBUG_KMS("\n")
[all...] |
| intel_psr.c | 132 DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
134 DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
136 DRM_DEBUG_KMS("\tPSR2 disabled\n");
138 DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
140 DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
142 DRM_DEBUG_KMS("\tGraphics reset\n");
144 DRM_DEBUG_KMS("\tPCH interrupt\n");
146 DRM_DEBUG_KMS("\tMemory up\n");
148 DRM_DEBUG_KMS("\tFront buffer modification\n");
150 DRM_DEBUG_KMS("\tPSR watchdog timer expired\n")
[all...] |
| intel_dsi.c | 42 DRM_DEBUG_KMS("\n");
45 DRM_DEBUG_KMS("no fixed mode\n");
52 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
68 DRM_DEBUG_KMS("\n");
|
| intel_hdcp.c | 64 DRM_DEBUG_KMS("Bksv is invalid\n");
480 DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
512 DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
531 DRM_DEBUG_KMS("KSV list failed to become ready (%d)\n", ret);
541 DRM_DEBUG_KMS("Max Topology Limit Exceeded\n");
554 DRM_DEBUG_KMS("Repeater with zero downstream devices\n");
560 DRM_DEBUG_KMS("Out of mem: ksv_fifo\n");
587 DRM_DEBUG_KMS("V Prime validation failed.(%d)\n", ret);
591 DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
640 DRM_DEBUG_KMS("Panel is not HDCP capable\n")
[all...] |
| intel_tc.c | 191 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
220 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
238 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
253 DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
268 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
293 DRM_DEBUG_KMS("Port %s: PHY not ready\n",
315 DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n",
321 DRM_DEBUG_KMS("Port %s: PHY max lanes %d < required lanes %d\n",
362 DRM_DEBUG_KMS("Port %s: PHY status not complete\n",
368 DRM_DEBUG_KMS("Port %s: PHY still in safe mode\n"
[all...] |
| dvo_ch7xxx.c | 172 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
198 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
226 DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s slave %d.\n",
237 DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s slave %d.\n",
243 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
347 DRM_DEBUG_KMS("\n %02X: ", i);
349 DRM_DEBUG_KMS("%02X ", val);
|
| intel_fbdev.c | 205 DRM_DEBUG_KMS("BIOS fb too small (%dx%d), we require (%dx%d),"
213 DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
219 DRM_DEBUG_KMS("re-using BIOS fb\n");
320 DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08"PRIx32"\n",
391 DRM_DEBUG_KMS("pipe %c not active or no fb, skipping\n",
397 DRM_DEBUG_KMS("found possible fb from plane %c\n",
405 DRM_DEBUG_KMS("no active fbs found, not using BIOS config\n");
416 DRM_DEBUG_KMS("pipe %c not active, skipping\n",
421 DRM_DEBUG_KMS("checking plane %c for BIOS fb\n",
432 DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n"
[all...] |
| vlv_dsi_pll.c | 134 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
146 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
157 DRM_DEBUG_KMS("\n");
182 DRM_DEBUG_KMS("DSI PLL locked\n");
190 DRM_DEBUG_KMS("\n");
244 DRM_DEBUG_KMS("\n");
271 DRM_DEBUG_KMS("\n");
489 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
515 DRM_DEBUG_KMS("\n");
541 DRM_DEBUG_KMS("DSI PLL locked\n")
[all...] |
| intel_dp.c | 474 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
484 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
527 DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
532 DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
542 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
576 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
595 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
774 DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
894 DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
1005 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n"
[all...] |
| intel_dsb.c | 62 DRM_DEBUG_KMS("DSB engine is busy.\n");
82 DRM_DEBUG_KMS("DSB engine is busy.\n");
213 DRM_DEBUG_KMS("DSB buffer overflow\n");
287 DRM_DEBUG_KMS("DSB buffer overflow\n");
334 DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_scdc_helper.c | 149 DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
176 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
187 DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret);
231 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
242 DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret);
|
| drm_dp_dual_mode_helper.c | 209 DRM_DEBUG_KMS("DP dual mode HDMI ID: %*pE (err %zd)\n",
228 DRM_DEBUG_KMS("DP dual mode adaptor ID: %02x (err %zd)\n",
292 DRM_DEBUG_KMS("Failed to query max TMDS clock\n");
331 DRM_DEBUG_KMS("Failed to query state of TMDS output buffers\n");
376 DRM_DEBUG_KMS("Failed to %s TMDS output buffers (%d attempts)\n",
385 DRM_DEBUG_KMS("I2C read failed during TMDS output buffer %s (%d attempts)\n",
395 DRM_DEBUG_KMS("I2C write value mismatch during TMDS output buffer %s\n",
466 DRM_DEBUG_KMS("LSPCON read(0x80, 0x41) failed\n");
521 DRM_DEBUG_KMS("LSPCON mode changed to %s\n",
|
| drm_crtc_helper.c | 339 DRM_DEBUG_KMS("Encoder fixup failed\n");
348 DRM_DEBUG_KMS("CRTC fixup failed\n");
352 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
391 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%s]\n",
542 DRM_DEBUG_KMS("\n");
561 DRM_DEBUG_KMS("[CRTC:%d:%s] [FB:%d] #connectors=%d (x y) (%i %i)\n",
566 DRM_DEBUG_KMS("[CRTC:%d:%s] [NOFB]\n",
617 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
629 DRM_DEBUG_KMS("modes are different, full mode set\n");
665 DRM_DEBUG_KMS("connector dpms not on, full mode switch\n")
[all...] |
| drm_client_modeset.c | 249 DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
310 DRM_DEBUG_KMS("can clone using command line\n");
335 DRM_DEBUG_KMS("can clone using 1024x768\n");
359 DRM_DEBUG_KMS("no modes for connector tiled %d %d\n", i,
371 DRM_DEBUG_KMS("returned %d %d for %d %d\n", hoffset, voffset, h_idx, v_idx);
428 DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n",
434 DRM_DEBUG_KMS("looking for preferred mode on connector %d %d\n",
457 DRM_DEBUG_KMS("Falling back to non tiled mode on Connector %d\n",
465 DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name :
623 DRM_DEBUG_KMS("connector %s not enabled, skipping\n"
[all...] |
| drm_framebuffer.c | 95 DRM_DEBUG_KMS("Invalid source coordinates "
188 DRM_DEBUG_KMS("bad framebuffer format %s\n",
198 DRM_DEBUG_KMS("bad framebuffer width %u\n", r->width);
203 DRM_DEBUG_KMS("bad framebuffer height %u\n", r->height);
214 DRM_DEBUG_KMS("Format requires non-linear modifier for plane %d\n", i);
219 DRM_DEBUG_KMS("no buffer object handle for plane %d\n", i);
230 DRM_DEBUG_KMS("bad pitch %u for plane %d\n", r->pitches[i], i);
235 DRM_DEBUG_KMS("bad fb modifier %"PRIu64" for plane %d\n",
242 DRM_DEBUG_KMS("bad fb modifier %"PRIu64" for plane %d\n",
256 DRM_DEBUG_KMS("bad modifier data for plane %d\n", i)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_dp_mst.c | 55 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
94 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
203 DRM_DEBUG_KMS("edid retrieved %p\n", edid);
296 DRM_DEBUG_KMS("\n");
331 DRM_DEBUG_KMS("\n");
353 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
379 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
418 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
448 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
529 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n"
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_irq.c | 125 DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
128 DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
191 DRM_DEBUG_KMS(
308 DRM_DEBUG_KMS(
379 DRM_DEBUG_KMS("DM_IRQ\n");
407 DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
430 DRM_DEBUG_KMS("DM_IRQ: suspend\n");
460 DRM_DEBUG_KMS("DM_IRQ: early resume\n");
483 DRM_DEBUG_KMS("DM_IRQ: resume\n");
|
