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    Searched refs:DReg (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
A15SDOptimizer.cpp 73 const DebugLoc &DL, unsigned DReg,
87 const DebugLoc &DL, unsigned DReg,
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
147 if (DReg != ARM::NoRegister) return ARM::ssub_1;
433 const DebugLoc &DL, unsigned DReg, unsigned Lane,
440 .addReg(DReg, 0, Lane);
478 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
484 .addReg(DReg)
ARMBaseInstrInfo.cpp 4960 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4963 if (DReg != ARM::NoRegister)
4964 return DReg;
4967 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4969 assert(DReg && "S-register with no D super-register?");
4970 return DReg;
4989 MachineInstr &MI, unsigned DReg,
4993 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4999 ImplicitSReg = TRI->getSubReg(DReg,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
Mips16FrameLowering.cpp 79 unsigned DReg = MRI->getDwarfRegNum(Reg, true);
81 MCCFIInstruction::createOffset(nullptr, DReg, Offset));
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/
M68kBaseInfo.h 61 DReg = 0x8,
M68kMCCodeEmitter.cpp 124 case M68kBeads::DReg:
355 case M68kBeads::DReg:
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/
M68kDisassembler.cpp 331 case M68kBeads::DReg:
336 if (Op != M68kBeads::Reg && Op != M68kBeads::DReg)
421 bool DA = (Op != M68kBeads::DReg) && Reader.readBits(1);
527 case M68kBeads::DReg:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FloatingPoint.cpp 907 unsigned DReg = countTrailingZeros(Defs);
908 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg
910 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
911 std::swap(RegMap[KReg], RegMap[DReg]);
913 Defs &= ~(1 << DReg);
939 unsigned DReg = countTrailingZeros(Defs);
940 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n");
942 pushReg(DReg);
943 Defs &= ~(1 << DReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 418 Register DReg = DstInst->getOperand(0).getReg();
423 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 4860 unsigned DReg = Inst.getOperand(0).getReg();
4863 unsigned TmpReg = DReg;
4869 if (DReg == SReg) {
4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4910 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4923 unsigned DReg = Inst.getOperand(0).getReg();
4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 8154 unsigned DReg = RISCV::F0_D + RegNo;
8155 return std::make_pair(DReg, &RISCV::FPR64RegClass);

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