Searched refs:DSC (Results 1 - 11 of 11) sorted by relevance

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
H A DMakefile34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
H A Damdgpu_dc_dsc.c37 /* default DSC policy target bitrate limit is 16bpp */
46 if (timing->flags.DSC) {
110 dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__);
126 dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__);
186 dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__);
215 dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__);
228 // This is a static HW query, so we can use any DSC
300 // TODO DSC: Remove this workaround for N422 and 420 once it's fixed, or move it to get_dsc_encoder_caps()
324 // Round down to the nearest precision stop to bring it into DSC spec range
332 /* Get DSC bandwidt
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_link_hwss.c387 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
413 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
432 /* Enable DSC hw block */
454 /* Enable DSC in encoder */
456 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
466 /* Enable DSC in OPTC */
467 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
474 /* disable DSC in OPTC */
479 /* disable DSC in stream encoder */
489 /* disable DSC bloc
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H A Damdgpu_dc_link.c3049 if (pipe_ctx->stream->timing.flags.DSC) {
3057 if (pipe_ctx->stream->timing.flags.DSC) {
3128 if (pipe_ctx->stream->timing.flags.DSC) {
3199 if (timing->flags.DSC) {
H A Damdgpu_dc.c2017 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2021 /* Use temporarry context for validating new DSC config */
2028 stream->timing.flags.DSC = enable_dsc;
2031 stream->timing.flags.DSC = old_dsc_enabled;
2037 DC_ERROR("Failed to allocate new validate context for DSC change\n");
/src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c560 params[i].timing->flags.DSC = 1;
563 params[i].timing->flags.DSC = 0;
767 stream->timing.flags.DSC = 0;
884 if (stream->timing.flags.DSC == 1)
H A Damdgpu_dm.c4095 stream->timing.flags.DSC = 0;
4115 stream->timing.flags.DSC = 1;
5017 if (stream->timing.flags.DSC != 1) {
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_hw_types.h679 uint32_t DSC : 1; /* Use DSC with this timing */ member in struct:dc_crtc_timing_flags
705 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
706 uint32_t num_slices_v; /* Number of DSC slices - vertical */
707 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
708 bool block_pred_enable; /* DSC block prediction enable */
709 uint32_t linebuf_depth; /* DSC line buffer depth */
710 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
711 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
712 int32_t rc_buffer_size; /* DSC R
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_stream_encoder.c275 /* Set DSC-related configuration.
276 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
446 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
H A Damdgpu_dcn20_resource.c1556 /* Find first free DSC */
1589 /* Get a DSC if required and available */
1645 /* Get a DSC if required and available */
1646 if (result == DC_OK && dc_stream->timing.flags.DSC)
1789 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1926 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2054 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2289 /* Validate DSC config, dsc count validation is already done */
2301 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_optc.c1517 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1520 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1523 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1531 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

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