| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| Makefile | 3 # Makefile for the 'dsc' sub-component of DAL.
30 CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
31 CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
32 CFLAGS_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_ccflags)
34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
|
| amdgpu_dc_dsc.c | 31 #include "dsc.h"
37 /* default DSC policy target bitrate limit is 16bpp */
46 if (timing->flags.DSC) {
110 dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__);
126 dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__);
186 dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__);
215 dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__);
224 const struct display_stream_compressor *dsc,
228 // This is a static HW query, so we can use any DSC
231 if (dsc) {
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_hwss.c | 20 #include "dsc.h"
378 dsc->ctx->logger
379 static void dsc_optc_config_log(struct display_stream_compressor *dsc,
387 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
413 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
418 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local in function:dp_set_dsc_on_stream
432 /* Enable DSC hw block */
441 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg)
498 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local in function:dp_set_dsc_enable
522 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local in function:dp_set_dsc_pps_sdp
566 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local in function:dp_update_dsc_config
[all...] |
| amdgpu_dc_link.c | 3049 if (pipe_ctx->stream->timing.flags.DSC) {
3057 if (pipe_ctx->stream->timing.flags.DSC) {
3128 if (pipe_ctx->stream->timing.flags.DSC) {
3199 if (timing->flags.DSC) {
|
| amdgpu_dc.c | 68 #include "dsc.h"
2017 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2021 /* Use temporarry context for validating new DSC config */
2028 stream->timing.flags.DSC = enable_dsc;
2031 stream->timing.flags.DSC = old_dsc_enabled;
2037 DC_ERROR("Failed to allocate new validate context for DSC change\n");
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_mst_types.c | 560 params[i].timing->flags.DSC = 1;
563 params[i].timing->flags.DSC = 0;
767 stream->timing.flags.DSC = 0;
884 if (stream->timing.flags.DSC == 1)
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| amdgpu_dm.c | 4095 stream->timing.flags.DSC = 0;
4115 stream->timing.flags.DSC = 1;
5017 if (stream->timing.flags.DSC != 1) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 679 uint32_t DSC : 1; /* Use DSC with this timing */
705 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
706 uint32_t num_slices_v; /* Number of DSC slices - vertical */
707 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
708 bool block_pred_enable; /* DSC block prediction enable */
709 uint32_t linebuf_depth; /* DSC line buffer depth */
710 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
711 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
712 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_stream_encoder.c | 275 /* Set DSC-related configuration.
276 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
347 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
354 //if dsc is enabled, continue to read
446 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
|
| amdgpu_dcn20_resource.c | 1295 struct dcn20_dsc *dsc = local in function:dcn20_dsc_create
1298 if (!dsc) {
1303 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1304 return &dsc->base;
1307 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1309 kfree(container_of(*dsc, struct dcn20_dsc, base));
1310 *dsc = NULL;
1542 struct display_stream_compressor **dsc,
1547 ASSERT(*dsc == NULL);
1548 *dsc = NULL
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_optc.c | 1517 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1520 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1523 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1531 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
|
