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    Searched refs:DSCC_INTERRUPT_CONTROL_STATUS (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_dsc.h	42 SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\ 467 uint32_t DSCC_INTERRUPT_CONTROL_STATUS;
amdgpu_dcn20_dsc.c	575 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,

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