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    Searched refs:DSCC_PPS_CONFIG4 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_dsc.h 47 SRI(DSCC_PPS_CONFIG4, DSCC, id),\
472 uint32_t DSCC_PPS_CONFIG4;
amdgpu_dcn20_dsc.c 608 REG_SET(DSCC_PPS_CONFIG4, 0,
728 * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder

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