1 /* $NetBSD: ds1307.c,v 1.43 2025/10/13 14:49:17 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.43 2025/10/13 14:49:17 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 #include "opt_dsrtc.h" 58 59 struct dsrtc_model { 60 const i2c_addr_t *dm_valid_addrs; 61 uint16_t dm_model; 62 uint8_t dm_ch_reg; 63 uint8_t dm_ch_value; 64 uint8_t dm_vbaten_reg; 65 uint8_t dm_vbaten_value; 66 uint8_t dm_rtc_start; 67 uint8_t dm_rtc_size; 68 uint8_t dm_nvram_start; 69 uint8_t dm_nvram_size; 70 uint8_t dm_flags; 71 #define DSRTC_FLAG_CLOCK_HOLD 0x01 72 #define DSRTC_FLAG_BCD 0x02 73 #define DSRTC_FLAG_TEMP 0x04 74 #define DSRTC_FLAG_VBATEN 0x08 75 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 76 }; 77 78 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 79 static const struct dsrtc_model ds1307_model = { 80 .dm_valid_addrs = ds1307_valid_addrs, 81 .dm_model = 1307, 82 .dm_ch_reg = DSXXXX_SECONDS, 83 .dm_ch_value = DS1307_SECONDS_CH, 84 .dm_rtc_start = DS1307_RTC_START, 85 .dm_rtc_size = DS1307_RTC_SIZE, 86 .dm_nvram_start = DS1307_NVRAM_START, 87 .dm_nvram_size = DS1307_NVRAM_SIZE, 88 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 89 }; 90 91 static const struct dsrtc_model ds1339_model = { 92 .dm_valid_addrs = ds1307_valid_addrs, 93 .dm_model = 1339, 94 .dm_rtc_start = DS1339_RTC_START, 95 .dm_rtc_size = DS1339_RTC_SIZE, 96 .dm_flags = DSRTC_FLAG_BCD, 97 }; 98 99 static const struct dsrtc_model ds1340_model = { 100 .dm_valid_addrs = ds1307_valid_addrs, 101 .dm_model = 1340, 102 .dm_ch_reg = DSXXXX_SECONDS, 103 .dm_ch_value = DS1340_SECONDS_EOSC, 104 .dm_rtc_start = DS1340_RTC_START, 105 .dm_rtc_size = DS1340_RTC_SIZE, 106 .dm_flags = DSRTC_FLAG_BCD, 107 }; 108 109 static const struct dsrtc_model ds1672_model = { 110 .dm_valid_addrs = ds1307_valid_addrs, 111 .dm_model = 1672, 112 .dm_rtc_start = DS1672_RTC_START, 113 .dm_rtc_size = DS1672_RTC_SIZE, 114 .dm_ch_reg = DS1672_CONTROL, 115 .dm_ch_value = DS1672_CONTROL_CH, 116 .dm_flags = 0, 117 }; 118 119 static const struct dsrtc_model ds3231_model = { 120 .dm_valid_addrs = ds1307_valid_addrs, 121 .dm_model = 3231, 122 .dm_rtc_start = DS3232_RTC_START, 123 .dm_rtc_size = DS3232_RTC_SIZE, 124 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 125 }; 126 127 static const struct dsrtc_model ds3232_model = { 128 .dm_valid_addrs = ds1307_valid_addrs, 129 .dm_model = 3232, 130 .dm_rtc_start = DS3232_RTC_START, 131 .dm_rtc_size = DS3232_RTC_SIZE, 132 .dm_nvram_start = DS3232_NVRAM_START, 133 .dm_nvram_size = DS3232_NVRAM_SIZE, 134 /* 135 * XXX 136 * the DS3232 likely has the temperature sensor too but I can't 137 * easily verify or test that right now 138 */ 139 .dm_flags = DSRTC_FLAG_BCD, 140 }; 141 142 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 143 static const struct dsrtc_model mcp7940_model = { 144 .dm_valid_addrs = mcp7940_valid_addrs, 145 .dm_model = 7940, 146 .dm_rtc_start = DS1307_RTC_START, 147 .dm_rtc_size = DS1307_RTC_SIZE, 148 .dm_ch_reg = DSXXXX_SECONDS, 149 .dm_ch_value = DS1307_SECONDS_CH, 150 .dm_vbaten_reg = DSXXXX_DAY, 151 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 152 .dm_nvram_start = MCP7940_NVRAM_START, 153 .dm_nvram_size = MCP7940_NVRAM_SIZE, 154 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 155 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 156 }; 157 158 static const struct device_compatible_entry compat_data[] = { 159 { .compat = "dallas,ds1307", .data = &ds1307_model }, 160 { .compat = "maxim,ds1307", .data = &ds1307_model }, 161 { .compat = "i2c-ds1307", .data = &ds1307_model }, 162 163 { .compat = "dallas,ds1339", .data = &ds1339_model }, 164 { .compat = "maxim,ds1339", .data = &ds1339_model }, 165 166 { .compat = "dallas,ds1340", .data = &ds1340_model }, 167 { .compat = "maxim,ds1340", .data = &ds1340_model }, 168 169 { .compat = "dallas,ds1672", .data = &ds1672_model }, 170 { .compat = "maxim,ds1672", .data = &ds1672_model }, 171 172 { .compat = "dallas,ds3231", .data = &ds3231_model }, 173 { .compat = "maxim,ds3231", .data = &ds3231_model }, 174 175 { .compat = "dallas,ds3232", .data = &ds3232_model }, 176 { .compat = "maxim,ds3232", .data = &ds3232_model }, 177 178 { .compat = "microchip,mcp7940", .data = &mcp7940_model }, 179 180 DEVICE_COMPAT_EOL 181 }; 182 183 struct dsrtc_softc { 184 device_t sc_dev; 185 i2c_tag_t sc_tag; 186 uint8_t sc_address; 187 bool sc_open; 188 struct dsrtc_model sc_model; 189 struct todr_chip_handle sc_todr; 190 struct sysmon_envsys *sc_sme; 191 envsys_data_t sc_sensor; 192 unsigned int sc_base_year; 193 }; 194 195 static void dsrtc_attach(device_t, device_t, void *); 196 static int dsrtc_match(device_t, cfdata_t, void *); 197 198 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 199 dsrtc_match, dsrtc_attach, NULL, NULL); 200 201 dev_type_open(dsrtc_open); 202 dev_type_close(dsrtc_close); 203 dev_type_read(dsrtc_read); 204 dev_type_write(dsrtc_write); 205 206 const struct cdevsw dsrtc_cdevsw = { 207 .d_open = dsrtc_open, 208 .d_close = dsrtc_close, 209 .d_read = dsrtc_read, 210 .d_write = dsrtc_write, 211 .d_ioctl = noioctl, 212 .d_stop = nostop, 213 .d_tty = notty, 214 .d_poll = nopoll, 215 .d_mmap = nommap, 216 .d_kqfilter = nokqfilter, 217 .d_discard = nodiscard, 218 .d_flag = D_OTHER 219 }; 220 221 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 222 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 223 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 224 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 225 226 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 227 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 228 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 229 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 230 231 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 232 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 233 234 static const struct dsrtc_model * 235 dsrtc_model_by_number(u_int model) 236 { 237 const struct device_compatible_entry *dce; 238 const struct dsrtc_model *dm; 239 240 /* no model given, assume it's a DS1307 */ 241 if (model == 0) 242 return &ds1307_model; 243 244 for (dce = compat_data; dce->compat != NULL; dce++) { 245 dm = dce->data; 246 if (dm->dm_model == model) 247 return dm; 248 } 249 return NULL; 250 } 251 252 static const struct dsrtc_model * 253 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 254 { 255 const struct dsrtc_model *dm = NULL; 256 const struct device_compatible_entry *dce; 257 258 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL) 259 dm = dce->data; 260 261 return dm; 262 } 263 264 static bool 265 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 266 { 267 268 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 269 if (addr == dm->dm_valid_addrs[i]) 270 return true; 271 } 272 return false; 273 } 274 275 static int 276 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 277 { 278 struct i2c_attach_args *ia = arg; 279 const struct dsrtc_model *dm; 280 int match_result; 281 282 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 283 return match_result; 284 285 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 286 if (dm == NULL) 287 return 0; 288 289 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 290 return I2C_MATCH_ADDRESS_ONLY; 291 292 return 0; 293 } 294 295 static void 296 dsrtc_attach(device_t parent, device_t self, void *arg) 297 { 298 struct dsrtc_softc *sc = device_private(self); 299 struct i2c_attach_args *ia = arg; 300 const struct dsrtc_model *dm; 301 302 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 303 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 304 305 if (dm == NULL) { 306 aprint_error(": unable to determine model!\n"); 307 return; 308 } 309 310 aprint_naive(": Real-time Clock%s\n", 311 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 312 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 313 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 314 315 sc->sc_tag = ia->ia_tag; 316 sc->sc_address = ia->ia_addr; 317 sc->sc_model = *dm; 318 sc->sc_dev = self; 319 sc->sc_open = 0; 320 sc->sc_todr.todr_dev = self; 321 322 if (dm->dm_flags & DSRTC_FLAG_BCD) { 323 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 324 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 325 } else { 326 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 327 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 328 } 329 330 sc->sc_base_year = device_getprop_uint_default(self, "start-year", 331 POSIX_BASE_YEAR); 332 333 todr_attach(&sc->sc_todr); 334 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 335 int error; 336 337 sc->sc_sme = sysmon_envsys_create(); 338 sc->sc_sme->sme_name = device_xname(self); 339 sc->sc_sme->sme_cookie = sc; 340 sc->sc_sme->sme_refresh = dsrtc_refresh; 341 342 sc->sc_sensor.units = ENVSYS_STEMP; 343 sc->sc_sensor.state = ENVSYS_SINVALID; 344 sc->sc_sensor.flags = 0; 345 (void)strlcpy(sc->sc_sensor.desc, "temperature", 346 sizeof(sc->sc_sensor.desc)); 347 348 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 349 aprint_error_dev(self, "unable to attach sensor\n"); 350 goto bad; 351 } 352 353 error = sysmon_envsys_register(sc->sc_sme); 354 if (error) { 355 aprint_error_dev(self, 356 "error %d registering with sysmon\n", error); 357 goto bad; 358 } 359 } 360 return; 361 bad: 362 sysmon_envsys_destroy(sc->sc_sme); 363 } 364 365 /*ARGSUSED*/ 366 int 367 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 368 { 369 struct dsrtc_softc *sc; 370 371 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 372 return ENXIO; 373 374 /* XXX: Locking */ 375 if (sc->sc_open) 376 return EBUSY; 377 378 sc->sc_open = true; 379 return 0; 380 } 381 382 /*ARGSUSED*/ 383 int 384 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 385 { 386 struct dsrtc_softc *sc; 387 388 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 389 return ENXIO; 390 391 sc->sc_open = false; 392 return 0; 393 } 394 395 /*ARGSUSED*/ 396 int 397 dsrtc_read(dev_t dev, struct uio *uio, int flags) 398 { 399 struct dsrtc_softc *sc; 400 int error; 401 402 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 403 return ENXIO; 404 405 const struct dsrtc_model * const dm = &sc->sc_model; 406 if (uio->uio_offset < 0 || uio->uio_offset >= dm->dm_nvram_size) 407 return EINVAL; 408 409 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 410 return error; 411 412 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 413 uint8_t ch, cmd; 414 const u_int a = uio->uio_offset; 415 cmd = a + dm->dm_nvram_start; 416 if ((error = iic_exec(sc->sc_tag, 417 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 418 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 419 iic_release_bus(sc->sc_tag, 0); 420 aprint_error_dev(sc->sc_dev, 421 "%s: read failed at 0x%x: %d\n", 422 __func__, a, error); 423 return error; 424 } 425 if ((error = uiomove(&ch, 1, uio)) != 0) { 426 iic_release_bus(sc->sc_tag, 0); 427 return error; 428 } 429 } 430 431 iic_release_bus(sc->sc_tag, 0); 432 433 return 0; 434 } 435 436 /*ARGSUSED*/ 437 int 438 dsrtc_write(dev_t dev, struct uio *uio, int flags) 439 { 440 struct dsrtc_softc *sc; 441 int error; 442 443 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 444 return ENXIO; 445 446 const struct dsrtc_model * const dm = &sc->sc_model; 447 if (uio->uio_offset >= dm->dm_nvram_size) 448 return EINVAL; 449 450 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 451 return error; 452 453 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 454 uint8_t cmdbuf[2]; 455 const u_int a = (int)uio->uio_offset; 456 cmdbuf[0] = a + dm->dm_nvram_start; 457 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 458 break; 459 460 if ((error = iic_exec(sc->sc_tag, 461 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 462 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 463 aprint_error_dev(sc->sc_dev, 464 "%s: write failed at 0x%x: %d\n", 465 __func__, a, error); 466 break; 467 } 468 } 469 470 iic_release_bus(sc->sc_tag, 0); 471 472 return error; 473 } 474 475 static int 476 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 477 { 478 struct dsrtc_softc *sc = device_private(ch->todr_dev); 479 struct clock_ymdhms check; 480 int retries; 481 482 memset(dt, 0, sizeof(*dt)); 483 memset(&check, 0, sizeof(check)); 484 485 /* 486 * Since we don't support Burst Read, we have to read the clock twice 487 * until we get two consecutive identical results. 488 */ 489 retries = 5; 490 do { 491 dsrtc_clock_read_ymdhms(sc, dt); 492 dsrtc_clock_read_ymdhms(sc, &check); 493 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 494 495 return 0; 496 } 497 498 static int 499 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 500 { 501 struct dsrtc_softc *sc = device_private(ch->todr_dev); 502 503 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 504 return -1; 505 506 return 0; 507 } 508 509 static int 510 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 511 { 512 struct dsrtc_model * const dm = &sc->sc_model; 513 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 514 int error; 515 516 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 517 518 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 519 aprint_error_dev(sc->sc_dev, 520 "%s: failed to acquire I2C bus: %d\n", 521 __func__, error); 522 return 0; 523 } 524 525 /* Read each RTC register in order. */ 526 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 527 cmdbuf[0] = dm->dm_rtc_start + i; 528 529 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 530 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0); 531 } 532 533 /* Done with I2C */ 534 iic_release_bus(sc->sc_tag, 0); 535 536 if (error != 0) { 537 aprint_error_dev(sc->sc_dev, 538 "%s: failed to read rtc at 0x%x: %d\n", 539 __func__, cmdbuf[0], error); 540 return 0; 541 } 542 543 /* 544 * Convert the RTC's register values into something useable 545 */ 546 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 547 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 548 549 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 550 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 551 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 552 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 553 dt->dt_hour += 12; 554 } else 555 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 556 DSXXXX_HOURS_24MASK); 557 558 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 559 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 560 561 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + sc->sc_base_year; 562 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) { 563 dt->dt_year += 100; 564 } 565 566 return 1; 567 } 568 569 static int 570 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 571 { 572 struct dsrtc_model * const dm = &sc->sc_model; 573 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 574 int error; 575 576 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 577 578 /* 579 * Convert our time representation into something the DSXXXX 580 * can understand. 581 */ 582 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 583 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 584 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 585 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 586 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 587 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 588 589 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - sc->sc_base_year) % 100); 590 if (dt->dt_year - sc->sc_base_year >= 100) 591 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 592 593 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 594 aprint_error_dev(sc->sc_dev, 595 "%s: failed to acquire I2C bus: %d\n", 596 __func__, error); 597 return 0; 598 } 599 600 /* Stop the clock */ 601 cmdbuf[0] = dm->dm_ch_reg; 602 603 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 604 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 605 iic_release_bus(sc->sc_tag, 0); 606 aprint_error_dev(sc->sc_dev, 607 "%s: failed to read Hold Clock: %d\n", 608 __func__, error); 609 return 0; 610 } 611 612 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 613 cmdbuf[1] &= ~dm->dm_ch_value; 614 else 615 cmdbuf[1] |= dm->dm_ch_value; 616 617 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 618 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 619 iic_release_bus(sc->sc_tag, 0); 620 aprint_error_dev(sc->sc_dev, 621 "%s: failed to write Hold Clock: %d\n", 622 __func__, error); 623 return 0; 624 } 625 626 /* 627 * Write registers in reverse order. The last write (to the Seconds 628 * register) will undo the Clock Hold, above. 629 */ 630 uint8_t op = I2C_OP_WRITE; 631 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 632 cmdbuf[0] = dm->dm_rtc_start + i; 633 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 634 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 635 bcd[i] |= dm->dm_vbaten_value; 636 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 637 op = I2C_OP_WRITE_WITH_STOP; 638 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 639 bcd[i] |= dm->dm_ch_value; 640 } 641 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 642 cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 643 iic_release_bus(sc->sc_tag, 0); 644 aprint_error_dev(sc->sc_dev, 645 "%s: failed to write rtc at 0x%x: %d\n", 646 __func__, i, error); 647 /* XXX: Clock Hold is likely still asserted! */ 648 return 0; 649 } 650 } 651 /* 652 * If the clock hold register isn't the same register as seconds, 653 * we need to reenable the clock. 654 */ 655 if (op != I2C_OP_WRITE_WITH_STOP) { 656 cmdbuf[0] = dm->dm_ch_reg; 657 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 658 cmdbuf[1] |= dm->dm_ch_value; 659 else 660 cmdbuf[1] &= ~dm->dm_ch_value; 661 662 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 663 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 664 iic_release_bus(sc->sc_tag, 0); 665 aprint_error_dev(sc->sc_dev, 666 "%s: failed to Hold Clock: %d\n", 667 __func__, error); 668 return 0; 669 } 670 } 671 672 iic_release_bus(sc->sc_tag, 0); 673 674 return 1; 675 } 676 677 static int 678 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 679 { 680 struct dsrtc_softc *sc = device_private(ch->todr_dev); 681 struct timeval check; 682 int retries; 683 684 memset(tv, 0, sizeof(*tv)); 685 memset(&check, 0, sizeof(check)); 686 687 /* 688 * Since we don't support Burst Read, we have to read the clock twice 689 * until we get two consecutive identical results. 690 */ 691 retries = 5; 692 do { 693 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 694 dsrtc_clock_read_timeval(sc, &check.tv_sec); 695 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 696 697 return 0; 698 } 699 700 static int 701 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 702 { 703 struct dsrtc_softc *sc = device_private(ch->todr_dev); 704 705 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 706 return -1; 707 708 return 0; 709 } 710 711 /* 712 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 713 * it, since some I2C controllers don't support anything other than single-byte 714 * transfers. 715 */ 716 static int 717 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 718 { 719 const struct dsrtc_model * const dm = &sc->sc_model; 720 uint8_t buf[4]; 721 int error; 722 723 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 724 aprint_error_dev(sc->sc_dev, 725 "%s: failed to acquire I2C bus: %d\n", 726 __func__, error); 727 return 0; 728 } 729 730 /* read all registers: */ 731 uint8_t reg = dm->dm_rtc_start; 732 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 733 ®, 1, buf, 4, 0); 734 735 /* Done with I2C */ 736 iic_release_bus(sc->sc_tag, 0); 737 738 if (error != 0) { 739 aprint_error_dev(sc->sc_dev, 740 "%s: failed to read rtc at 0x%x: %d\n", 741 __func__, reg, error); 742 return 0; 743 } 744 745 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 746 *tp = v; 747 748 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 749 __func__, v); 750 751 return 1; 752 } 753 754 static int 755 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 756 { 757 const struct dsrtc_model * const dm = &sc->sc_model; 758 size_t buflen = dm->dm_rtc_size + 2; 759 /* XXX: the biggest dm_rtc_size we have now is 7, so we should be ok */ 760 uint8_t buf[16]; 761 int error; 762 763 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 764 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 765 766 buf[0] = dm->dm_rtc_start; 767 buf[1] = (t >> 0) & 0xff; 768 buf[2] = (t >> 8) & 0xff; 769 buf[3] = (t >> 16) & 0xff; 770 buf[4] = (t >> 24) & 0xff; 771 buf[5] = 0; 772 773 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 774 aprint_error_dev(sc->sc_dev, 775 "%s: failed to acquire I2C bus: %d\n", 776 __func__, error); 777 return 0; 778 } 779 780 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 781 &buf, buflen, NULL, 0, 0); 782 783 /* Done with I2C */ 784 iic_release_bus(sc->sc_tag, 0); 785 786 /* send data */ 787 if (error != 0) { 788 aprint_error_dev(sc->sc_dev, 789 "%s: failed to set time: %d\n", 790 __func__, error); 791 return 0; 792 } 793 794 return 1; 795 } 796 797 static int 798 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 799 { 800 int error, tc; 801 uint8_t reg = DS3232_TEMP_MSB; 802 uint8_t buf[2]; 803 804 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 805 return ENOTSUP; 806 807 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 808 aprint_error_dev(sc->sc_dev, 809 "%s: failed to acquire I2C bus: %d\n", 810 __func__, error); 811 return 0; 812 } 813 814 /* read temperature registers: */ 815 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 816 ®, 1, buf, 2, 0); 817 818 /* Done with I2C */ 819 iic_release_bus(sc->sc_tag, 0); 820 821 if (error != 0) { 822 aprint_error_dev(sc->sc_dev, 823 "%s: failed to read temperature: %d\n", 824 __func__, error); 825 return 0; 826 } 827 828 /* convert to microkelvin */ 829 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 830 *temp = tc + 273150000; 831 return 1; 832 } 833 834 static void 835 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 836 { 837 struct dsrtc_softc *sc = sme->sme_cookie; 838 uint32_t temp = 0; /* XXX gcc */ 839 840 if (dsrtc_read_temp(sc, &temp) == 0) { 841 edata->state = ENVSYS_SINVALID; 842 return; 843 } 844 845 edata->value_cur = temp; 846 847 edata->state = ENVSYS_SVALID; 848 } 849
Indexes created Tue Oct 14 01:09:49 GMT 2025