1 /* $NetBSD: ds1307.c,v 1.44 2025/10/14 09:19:48 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.44 2025/10/14 09:19:48 tnn Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 58 struct dsrtc_model { 59 const i2c_addr_t *dm_valid_addrs; 60 uint16_t dm_model; 61 uint8_t dm_ch_reg; 62 uint8_t dm_ch_value; 63 uint8_t dm_vbaten_reg; 64 uint8_t dm_vbaten_value; 65 uint8_t dm_rtc_start; 66 uint8_t dm_rtc_size; 67 uint8_t dm_nvram_start; 68 uint8_t dm_nvram_size; 69 uint8_t dm_flags; 70 #define DSRTC_FLAG_CLOCK_HOLD 0x01 71 #define DSRTC_FLAG_BCD 0x02 72 #define DSRTC_FLAG_TEMP 0x04 73 #define DSRTC_FLAG_VBATEN 0x08 74 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 75 }; 76 77 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 78 static const struct dsrtc_model ds1307_model = { 79 .dm_valid_addrs = ds1307_valid_addrs, 80 .dm_model = 1307, 81 .dm_ch_reg = DSXXXX_SECONDS, 82 .dm_ch_value = DS1307_SECONDS_CH, 83 .dm_rtc_start = DS1307_RTC_START, 84 .dm_rtc_size = DS1307_RTC_SIZE, 85 .dm_nvram_start = DS1307_NVRAM_START, 86 .dm_nvram_size = DS1307_NVRAM_SIZE, 87 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 88 }; 89 90 static const struct dsrtc_model ds1339_model = { 91 .dm_valid_addrs = ds1307_valid_addrs, 92 .dm_model = 1339, 93 .dm_rtc_start = DS1339_RTC_START, 94 .dm_rtc_size = DS1339_RTC_SIZE, 95 .dm_flags = DSRTC_FLAG_BCD, 96 }; 97 98 static const struct dsrtc_model ds1340_model = { 99 .dm_valid_addrs = ds1307_valid_addrs, 100 .dm_model = 1340, 101 .dm_ch_reg = DSXXXX_SECONDS, 102 .dm_ch_value = DS1340_SECONDS_EOSC, 103 .dm_rtc_start = DS1340_RTC_START, 104 .dm_rtc_size = DS1340_RTC_SIZE, 105 .dm_flags = DSRTC_FLAG_BCD, 106 }; 107 108 static const struct dsrtc_model ds1672_model = { 109 .dm_valid_addrs = ds1307_valid_addrs, 110 .dm_model = 1672, 111 .dm_rtc_start = DS1672_RTC_START, 112 .dm_rtc_size = DS1672_RTC_SIZE, 113 .dm_ch_reg = DS1672_CONTROL, 114 .dm_ch_value = DS1672_CONTROL_CH, 115 .dm_flags = 0, 116 }; 117 118 static const struct dsrtc_model ds3231_model = { 119 .dm_valid_addrs = ds1307_valid_addrs, 120 .dm_model = 3231, 121 .dm_rtc_start = DS3232_RTC_START, 122 .dm_rtc_size = DS3232_RTC_SIZE, 123 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 124 }; 125 126 static const struct dsrtc_model ds3232_model = { 127 .dm_valid_addrs = ds1307_valid_addrs, 128 .dm_model = 3232, 129 .dm_rtc_start = DS3232_RTC_START, 130 .dm_rtc_size = DS3232_RTC_SIZE, 131 .dm_nvram_start = DS3232_NVRAM_START, 132 .dm_nvram_size = DS3232_NVRAM_SIZE, 133 /* 134 * XXX 135 * the DS3232 likely has the temperature sensor too but I can't 136 * easily verify or test that right now 137 */ 138 .dm_flags = DSRTC_FLAG_BCD, 139 }; 140 141 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 142 static const struct dsrtc_model mcp7940_model = { 143 .dm_valid_addrs = mcp7940_valid_addrs, 144 .dm_model = 7940, 145 .dm_rtc_start = DS1307_RTC_START, 146 .dm_rtc_size = DS1307_RTC_SIZE, 147 .dm_ch_reg = DSXXXX_SECONDS, 148 .dm_ch_value = DS1307_SECONDS_CH, 149 .dm_vbaten_reg = DSXXXX_DAY, 150 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 151 .dm_nvram_start = MCP7940_NVRAM_START, 152 .dm_nvram_size = MCP7940_NVRAM_SIZE, 153 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 154 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 155 }; 156 157 static const struct device_compatible_entry compat_data[] = { 158 { .compat = "dallas,ds1307", .data = &ds1307_model }, 159 { .compat = "maxim,ds1307", .data = &ds1307_model }, 160 { .compat = "i2c-ds1307", .data = &ds1307_model }, 161 162 { .compat = "dallas,ds1339", .data = &ds1339_model }, 163 { .compat = "maxim,ds1339", .data = &ds1339_model }, 164 165 { .compat = "dallas,ds1340", .data = &ds1340_model }, 166 { .compat = "maxim,ds1340", .data = &ds1340_model }, 167 168 { .compat = "dallas,ds1672", .data = &ds1672_model }, 169 { .compat = "maxim,ds1672", .data = &ds1672_model }, 170 171 { .compat = "dallas,ds3231", .data = &ds3231_model }, 172 { .compat = "maxim,ds3231", .data = &ds3231_model }, 173 174 { .compat = "dallas,ds3232", .data = &ds3232_model }, 175 { .compat = "maxim,ds3232", .data = &ds3232_model }, 176 177 { .compat = "microchip,mcp7940", .data = &mcp7940_model }, 178 179 DEVICE_COMPAT_EOL 180 }; 181 182 struct dsrtc_softc { 183 device_t sc_dev; 184 i2c_tag_t sc_tag; 185 uint8_t sc_address; 186 bool sc_open; 187 struct dsrtc_model sc_model; 188 struct todr_chip_handle sc_todr; 189 struct sysmon_envsys *sc_sme; 190 envsys_data_t sc_sensor; 191 unsigned int sc_base_year; 192 }; 193 194 static void dsrtc_attach(device_t, device_t, void *); 195 static int dsrtc_match(device_t, cfdata_t, void *); 196 197 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 198 dsrtc_match, dsrtc_attach, NULL, NULL); 199 200 dev_type_open(dsrtc_open); 201 dev_type_close(dsrtc_close); 202 dev_type_read(dsrtc_read); 203 dev_type_write(dsrtc_write); 204 205 const struct cdevsw dsrtc_cdevsw = { 206 .d_open = dsrtc_open, 207 .d_close = dsrtc_close, 208 .d_read = dsrtc_read, 209 .d_write = dsrtc_write, 210 .d_ioctl = noioctl, 211 .d_stop = nostop, 212 .d_tty = notty, 213 .d_poll = nopoll, 214 .d_mmap = nommap, 215 .d_kqfilter = nokqfilter, 216 .d_discard = nodiscard, 217 .d_flag = D_OTHER 218 }; 219 220 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 221 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 222 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 223 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 224 225 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 226 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 227 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 228 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 229 230 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 231 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 232 233 static const struct dsrtc_model * 234 dsrtc_model_by_number(u_int model) 235 { 236 const struct device_compatible_entry *dce; 237 const struct dsrtc_model *dm; 238 239 /* no model given, assume it's a DS1307 */ 240 if (model == 0) 241 return &ds1307_model; 242 243 for (dce = compat_data; dce->compat != NULL; dce++) { 244 dm = dce->data; 245 if (dm->dm_model == model) 246 return dm; 247 } 248 return NULL; 249 } 250 251 static const struct dsrtc_model * 252 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 253 { 254 const struct dsrtc_model *dm = NULL; 255 const struct device_compatible_entry *dce; 256 257 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL) 258 dm = dce->data; 259 260 return dm; 261 } 262 263 static bool 264 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 265 { 266 267 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 268 if (addr == dm->dm_valid_addrs[i]) 269 return true; 270 } 271 return false; 272 } 273 274 static int 275 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 276 { 277 struct i2c_attach_args *ia = arg; 278 const struct dsrtc_model *dm; 279 int match_result; 280 281 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 282 return match_result; 283 284 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 285 if (dm == NULL) 286 return 0; 287 288 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 289 return I2C_MATCH_ADDRESS_ONLY; 290 291 return 0; 292 } 293 294 static void 295 dsrtc_attach(device_t parent, device_t self, void *arg) 296 { 297 struct dsrtc_softc *sc = device_private(self); 298 struct i2c_attach_args *ia = arg; 299 const struct dsrtc_model *dm; 300 301 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 302 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 303 304 if (dm == NULL) { 305 aprint_error(": unable to determine model!\n"); 306 return; 307 } 308 309 aprint_naive(": Real-time Clock%s\n", 310 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 311 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 312 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 313 314 sc->sc_tag = ia->ia_tag; 315 sc->sc_address = ia->ia_addr; 316 sc->sc_model = *dm; 317 sc->sc_dev = self; 318 sc->sc_open = 0; 319 sc->sc_todr.todr_dev = self; 320 321 if (dm->dm_flags & DSRTC_FLAG_BCD) { 322 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 323 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 324 } else { 325 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 326 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 327 } 328 329 sc->sc_base_year = device_getprop_uint_default(self, "start-year", 330 POSIX_BASE_YEAR); 331 332 todr_attach(&sc->sc_todr); 333 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 334 int error; 335 336 sc->sc_sme = sysmon_envsys_create(); 337 sc->sc_sme->sme_name = device_xname(self); 338 sc->sc_sme->sme_cookie = sc; 339 sc->sc_sme->sme_refresh = dsrtc_refresh; 340 341 sc->sc_sensor.units = ENVSYS_STEMP; 342 sc->sc_sensor.state = ENVSYS_SINVALID; 343 sc->sc_sensor.flags = 0; 344 (void)strlcpy(sc->sc_sensor.desc, "temperature", 345 sizeof(sc->sc_sensor.desc)); 346 347 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 348 aprint_error_dev(self, "unable to attach sensor\n"); 349 goto bad; 350 } 351 352 error = sysmon_envsys_register(sc->sc_sme); 353 if (error) { 354 aprint_error_dev(self, 355 "error %d registering with sysmon\n", error); 356 goto bad; 357 } 358 } 359 return; 360 bad: 361 sysmon_envsys_destroy(sc->sc_sme); 362 } 363 364 /*ARGSUSED*/ 365 int 366 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 367 { 368 struct dsrtc_softc *sc; 369 370 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 371 return ENXIO; 372 373 /* XXX: Locking */ 374 if (sc->sc_open) 375 return EBUSY; 376 377 sc->sc_open = true; 378 return 0; 379 } 380 381 /*ARGSUSED*/ 382 int 383 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 384 { 385 struct dsrtc_softc *sc; 386 387 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 388 return ENXIO; 389 390 sc->sc_open = false; 391 return 0; 392 } 393 394 /*ARGSUSED*/ 395 int 396 dsrtc_read(dev_t dev, struct uio *uio, int flags) 397 { 398 struct dsrtc_softc *sc; 399 int error; 400 401 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 402 return ENXIO; 403 404 const struct dsrtc_model * const dm = &sc->sc_model; 405 if (uio->uio_offset < 0 || uio->uio_offset >= dm->dm_nvram_size) 406 return EINVAL; 407 408 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 409 return error; 410 411 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 412 uint8_t ch, cmd; 413 const u_int a = uio->uio_offset; 414 cmd = a + dm->dm_nvram_start; 415 if ((error = iic_exec(sc->sc_tag, 416 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 417 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 418 iic_release_bus(sc->sc_tag, 0); 419 aprint_error_dev(sc->sc_dev, 420 "%s: read failed at 0x%x: %d\n", 421 __func__, a, error); 422 return error; 423 } 424 if ((error = uiomove(&ch, 1, uio)) != 0) { 425 iic_release_bus(sc->sc_tag, 0); 426 return error; 427 } 428 } 429 430 iic_release_bus(sc->sc_tag, 0); 431 432 return 0; 433 } 434 435 /*ARGSUSED*/ 436 int 437 dsrtc_write(dev_t dev, struct uio *uio, int flags) 438 { 439 struct dsrtc_softc *sc; 440 int error; 441 442 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 443 return ENXIO; 444 445 const struct dsrtc_model * const dm = &sc->sc_model; 446 if (uio->uio_offset >= dm->dm_nvram_size) 447 return EINVAL; 448 449 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 450 return error; 451 452 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 453 uint8_t cmdbuf[2]; 454 const u_int a = (int)uio->uio_offset; 455 cmdbuf[0] = a + dm->dm_nvram_start; 456 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 457 break; 458 459 if ((error = iic_exec(sc->sc_tag, 460 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 461 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 462 aprint_error_dev(sc->sc_dev, 463 "%s: write failed at 0x%x: %d\n", 464 __func__, a, error); 465 break; 466 } 467 } 468 469 iic_release_bus(sc->sc_tag, 0); 470 471 return error; 472 } 473 474 static int 475 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 476 { 477 struct dsrtc_softc *sc = device_private(ch->todr_dev); 478 struct clock_ymdhms check; 479 int retries; 480 481 memset(dt, 0, sizeof(*dt)); 482 memset(&check, 0, sizeof(check)); 483 484 /* 485 * Since we don't support Burst Read, we have to read the clock twice 486 * until we get two consecutive identical results. 487 */ 488 retries = 5; 489 do { 490 dsrtc_clock_read_ymdhms(sc, dt); 491 dsrtc_clock_read_ymdhms(sc, &check); 492 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 493 494 return 0; 495 } 496 497 static int 498 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 499 { 500 struct dsrtc_softc *sc = device_private(ch->todr_dev); 501 502 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 503 return -1; 504 505 return 0; 506 } 507 508 static int 509 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 510 { 511 struct dsrtc_model * const dm = &sc->sc_model; 512 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 513 int error; 514 515 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 516 517 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 518 aprint_error_dev(sc->sc_dev, 519 "%s: failed to acquire I2C bus: %d\n", 520 __func__, error); 521 return 0; 522 } 523 524 /* Read each RTC register in order. */ 525 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 526 cmdbuf[0] = dm->dm_rtc_start + i; 527 528 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 529 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0); 530 } 531 532 /* Done with I2C */ 533 iic_release_bus(sc->sc_tag, 0); 534 535 if (error != 0) { 536 aprint_error_dev(sc->sc_dev, 537 "%s: failed to read rtc at 0x%x: %d\n", 538 __func__, cmdbuf[0], error); 539 return 0; 540 } 541 542 /* 543 * Convert the RTC's register values into something useable 544 */ 545 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 546 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 547 548 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 549 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 550 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 551 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 552 dt->dt_hour += 12; 553 } else 554 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 555 DSXXXX_HOURS_24MASK); 556 557 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 558 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 559 560 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + sc->sc_base_year; 561 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) { 562 dt->dt_year += 100; 563 } 564 565 return 1; 566 } 567 568 static int 569 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 570 { 571 struct dsrtc_model * const dm = &sc->sc_model; 572 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 573 int error; 574 575 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 576 577 /* 578 * Convert our time representation into something the DSXXXX 579 * can understand. 580 */ 581 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 582 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 583 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 584 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 585 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 586 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 587 588 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - sc->sc_base_year) % 100); 589 if (dt->dt_year - sc->sc_base_year >= 100) 590 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 591 592 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 593 aprint_error_dev(sc->sc_dev, 594 "%s: failed to acquire I2C bus: %d\n", 595 __func__, error); 596 return 0; 597 } 598 599 /* Stop the clock */ 600 cmdbuf[0] = dm->dm_ch_reg; 601 602 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 603 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 604 iic_release_bus(sc->sc_tag, 0); 605 aprint_error_dev(sc->sc_dev, 606 "%s: failed to read Hold Clock: %d\n", 607 __func__, error); 608 return 0; 609 } 610 611 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 612 cmdbuf[1] &= ~dm->dm_ch_value; 613 else 614 cmdbuf[1] |= dm->dm_ch_value; 615 616 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 617 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 618 iic_release_bus(sc->sc_tag, 0); 619 aprint_error_dev(sc->sc_dev, 620 "%s: failed to write Hold Clock: %d\n", 621 __func__, error); 622 return 0; 623 } 624 625 /* 626 * Write registers in reverse order. The last write (to the Seconds 627 * register) will undo the Clock Hold, above. 628 */ 629 uint8_t op = I2C_OP_WRITE; 630 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 631 cmdbuf[0] = dm->dm_rtc_start + i; 632 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 633 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 634 bcd[i] |= dm->dm_vbaten_value; 635 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 636 op = I2C_OP_WRITE_WITH_STOP; 637 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 638 bcd[i] |= dm->dm_ch_value; 639 } 640 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 641 cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 642 iic_release_bus(sc->sc_tag, 0); 643 aprint_error_dev(sc->sc_dev, 644 "%s: failed to write rtc at 0x%x: %d\n", 645 __func__, i, error); 646 /* XXX: Clock Hold is likely still asserted! */ 647 return 0; 648 } 649 } 650 /* 651 * If the clock hold register isn't the same register as seconds, 652 * we need to reenable the clock. 653 */ 654 if (op != I2C_OP_WRITE_WITH_STOP) { 655 cmdbuf[0] = dm->dm_ch_reg; 656 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 657 cmdbuf[1] |= dm->dm_ch_value; 658 else 659 cmdbuf[1] &= ~dm->dm_ch_value; 660 661 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 662 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 663 iic_release_bus(sc->sc_tag, 0); 664 aprint_error_dev(sc->sc_dev, 665 "%s: failed to Hold Clock: %d\n", 666 __func__, error); 667 return 0; 668 } 669 } 670 671 iic_release_bus(sc->sc_tag, 0); 672 673 return 1; 674 } 675 676 static int 677 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 678 { 679 struct dsrtc_softc *sc = device_private(ch->todr_dev); 680 struct timeval check; 681 int retries; 682 683 memset(tv, 0, sizeof(*tv)); 684 memset(&check, 0, sizeof(check)); 685 686 /* 687 * Since we don't support Burst Read, we have to read the clock twice 688 * until we get two consecutive identical results. 689 */ 690 retries = 5; 691 do { 692 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 693 dsrtc_clock_read_timeval(sc, &check.tv_sec); 694 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 695 696 return 0; 697 } 698 699 static int 700 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 701 { 702 struct dsrtc_softc *sc = device_private(ch->todr_dev); 703 704 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 705 return -1; 706 707 return 0; 708 } 709 710 /* 711 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 712 * it, since some I2C controllers don't support anything other than single-byte 713 * transfers. 714 */ 715 static int 716 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 717 { 718 const struct dsrtc_model * const dm = &sc->sc_model; 719 uint8_t buf[4]; 720 int error; 721 722 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 723 aprint_error_dev(sc->sc_dev, 724 "%s: failed to acquire I2C bus: %d\n", 725 __func__, error); 726 return 0; 727 } 728 729 /* read all registers: */ 730 uint8_t reg = dm->dm_rtc_start; 731 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 732 ®, 1, buf, 4, 0); 733 734 /* Done with I2C */ 735 iic_release_bus(sc->sc_tag, 0); 736 737 if (error != 0) { 738 aprint_error_dev(sc->sc_dev, 739 "%s: failed to read rtc at 0x%x: %d\n", 740 __func__, reg, error); 741 return 0; 742 } 743 744 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 745 *tp = v; 746 747 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 748 __func__, v); 749 750 return 1; 751 } 752 753 static int 754 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 755 { 756 const struct dsrtc_model * const dm = &sc->sc_model; 757 size_t buflen = dm->dm_rtc_size + 2; 758 /* XXX: the biggest dm_rtc_size we have now is 7, so we should be ok */ 759 uint8_t buf[16]; 760 int error; 761 762 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 763 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 764 765 buf[0] = dm->dm_rtc_start; 766 buf[1] = (t >> 0) & 0xff; 767 buf[2] = (t >> 8) & 0xff; 768 buf[3] = (t >> 16) & 0xff; 769 buf[4] = (t >> 24) & 0xff; 770 buf[5] = 0; 771 772 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 773 aprint_error_dev(sc->sc_dev, 774 "%s: failed to acquire I2C bus: %d\n", 775 __func__, error); 776 return 0; 777 } 778 779 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 780 &buf, buflen, NULL, 0, 0); 781 782 /* Done with I2C */ 783 iic_release_bus(sc->sc_tag, 0); 784 785 /* send data */ 786 if (error != 0) { 787 aprint_error_dev(sc->sc_dev, 788 "%s: failed to set time: %d\n", 789 __func__, error); 790 return 0; 791 } 792 793 return 1; 794 } 795 796 static int 797 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 798 { 799 int error, tc; 800 uint8_t reg = DS3232_TEMP_MSB; 801 uint8_t buf[2]; 802 803 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 804 return ENOTSUP; 805 806 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 807 aprint_error_dev(sc->sc_dev, 808 "%s: failed to acquire I2C bus: %d\n", 809 __func__, error); 810 return 0; 811 } 812 813 /* read temperature registers: */ 814 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 815 ®, 1, buf, 2, 0); 816 817 /* Done with I2C */ 818 iic_release_bus(sc->sc_tag, 0); 819 820 if (error != 0) { 821 aprint_error_dev(sc->sc_dev, 822 "%s: failed to read temperature: %d\n", 823 __func__, error); 824 return 0; 825 } 826 827 /* convert to microkelvin */ 828 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 829 *temp = tc + 273150000; 830 return 1; 831 } 832 833 static void 834 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 835 { 836 struct dsrtc_softc *sc = sme->sme_cookie; 837 uint32_t temp = 0; /* XXX gcc */ 838 839 if (dsrtc_read_temp(sc, &temp) == 0) { 840 edata->state = ENVSYS_SINVALID; 841 return; 842 } 843 844 edata->value_cur = temp; 845 846 edata->state = ENVSYS_SVALID; 847 } 848
Indexes created Wed Oct 15 03:09:54 GMT 2025