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    Searched refs:DVMM_PTE_CONTROL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_mem_input.h 60 SRI(DVMM_PTE_CONTROL, DCP, id),\
99 uint32_t DVMM_PTE_CONTROL;
171 SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
172 SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
173 SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
amdgpu_dce_mem_input.c 158 REG_UPDATE_3(DVMM_PTE_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 137 DVMM_PTE_CONTROL,
143 DVMM_PTE_CONTROL,
149 DVMM_PTE_CONTROL,

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