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| /src/sys/arch/mips/cavium/dev/ | |
| octeon_xhcireg.h | 78 #define DWC3_GCTL_DSBLCLKGTNG 0x00000001u |
| octeon_xhci.c | 373 val |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 375 val &= ~DWC3_GCTL_DSBLCLKGTNG; |