1 /* $NetBSD: dwcdmacreg.h,v 1.1 2026/06/14 00:02:35 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2024, 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare AHB Central DMA Controller (dw_dmac). 33 * 34 * Register layout is generic to the core; this copy lives here for the 35 * 460EX integration, where one dedicated instance sits on the AHB just 36 * below the DWC SATA core and feeds its DMADR FIFO window through the 37 * hardware handshake interface. 38 * 39 * This should probably go to sys/dev/ic/, when someone else needs it. 40 */ 41 42 #ifndef _IBM4XX_DWCDMACREG_H_ 43 #define _IBM4XX_DWCDMACREG_H_ 44 45 #define DWCDMAC_SIZE 0x400 46 /* offset of the DMAC below the SATA core on the 460EX AHB */ 47 #define DWCDMAC_OFFSET 0x800 48 49 /* per-channel register block, ch = 0..7 */ 50 #define DWCDMAC_CHAN_SIZE 0x58 51 #define DWCDMAC_CHAN(ch) ((ch) * DWCDMAC_CHAN_SIZE) 52 #define DWCDMAC_SAR(ch) (DWCDMAC_CHAN(ch) + 0x00) /* source addr */ 53 #define DWCDMAC_DAR(ch) (DWCDMAC_CHAN(ch) + 0x08) /* dest addr */ 54 #define DWCDMAC_LLP(ch) (DWCDMAC_CHAN(ch) + 0x10) /* list pointer */ 55 #define DWCDMAC_CTL(ch) (DWCDMAC_CHAN(ch) + 0x18) /* control, low */ 56 #define DWCDMAC_CTL_HI(ch) (DWCDMAC_CHAN(ch) + 0x1c) /* control, high */ 57 #define DWCDMAC_SSTAT(ch) (DWCDMAC_CHAN(ch) + 0x20) 58 #define DWCDMAC_DSTAT(ch) (DWCDMAC_CHAN(ch) + 0x28) 59 #define DWCDMAC_SSTATAR(ch) (DWCDMAC_CHAN(ch) + 0x30) 60 #define DWCDMAC_DSTATAR(ch) (DWCDMAC_CHAN(ch) + 0x38) 61 #define DWCDMAC_CFG(ch) (DWCDMAC_CHAN(ch) + 0x40) /* config, low */ 62 #define DWCDMAC_CFG_HI(ch) (DWCDMAC_CHAN(ch) + 0x44) /* config, high */ 63 #define DWCDMAC_SGR(ch) (DWCDMAC_CHAN(ch) + 0x48) 64 #define DWCDMAC_DSR(ch) (DWCDMAC_CHAN(ch) + 0x50) 65 66 /* 67 * Interrupt registers, one channel bit each. RAW latches regardless of 68 * MASK_*; STATUS_* is RAW & MASK; CLEAR_* is write-1-to-clear. 69 */ 70 #define DWCDMAC_RAW_TFR 0x2c0 /* DMA (chain) transfer complete */ 71 #define DWCDMAC_RAW_BLOCK 0x2c8 /* block transfer complete */ 72 #define DWCDMAC_RAW_SRCTRAN 0x2d0 73 #define DWCDMAC_RAW_DSTTRAN 0x2d8 74 #define DWCDMAC_RAW_ERR 0x2e0 /* AHB error response */ 75 #define DWCDMAC_STATUS_TFR 0x2e8 76 #define DWCDMAC_STATUS_BLOCK 0x2f0 77 #define DWCDMAC_STATUS_SRCTRAN 0x2f8 78 #define DWCDMAC_STATUS_DSTTRAN 0x300 79 #define DWCDMAC_STATUS_ERR 0x308 80 #define DWCDMAC_MASK_TFR 0x310 /* write-enable scheme, see below */ 81 #define DWCDMAC_MASK_BLOCK 0x318 82 #define DWCDMAC_MASK_SRCTRAN 0x320 83 #define DWCDMAC_MASK_DSTTRAN 0x328 84 #define DWCDMAC_MASK_ERR 0x330 85 #define DWCDMAC_CLEAR_TFR 0x338 86 #define DWCDMAC_CLEAR_BLOCK 0x340 87 #define DWCDMAC_CLEAR_SRCTRAN 0x348 88 #define DWCDMAC_CLEAR_DSTTRAN 0x350 89 #define DWCDMAC_CLEAR_ERR 0x358 90 #define DWCDMAC_STATUSINT 0x360 /* combined status, read-only */ 91 92 /* software handshake request registers; unused (hardware handshake) */ 93 #define DWCDMAC_REQ_SRC 0x368 94 #define DWCDMAC_REQ_DST 0x370 95 #define DWCDMAC_SGL_REQ_SRC 0x378 96 #define DWCDMAC_SGL_REQ_DST 0x380 97 #define DWCDMAC_LST_SRC 0x388 98 #define DWCDMAC_LST_DST 0x390 99 100 #define DWCDMAC_DMACFG 0x398 /* global configuration */ 101 #define DWCDMAC_DMACFG_EN 0x00000001 102 #define DWCDMAC_CHEN 0x3a0 /* channel enable */ 103 #define DWCDMAC_ID 0x3a8 104 #define DWCDMAC_TEST 0x3b0 105 /* 0x3c8-0x3f7: component parameter registers, unused */ 106 107 /* 108 * CHEN and MASK_* use a write-enable scheme: bits 15:8 select which of 109 * the channel bits 7:0 a write actually affects. A channel's CHEN bit 110 * self-clears when its transfer (chain) completes. 111 */ 112 #define DWCDMAC_CHANBIT(ch) (1U << (ch)) 113 #define DWCDMAC_CH_ENABLE(ch) (DWCDMAC_CHANBIT(ch) | (DWCDMAC_CHANBIT(ch) << 8)) 114 #define DWCDMAC_CH_DISABLE(ch) (DWCDMAC_CHANBIT(ch) << 8) 115 116 /* CTL, low word */ 117 #define DWCDMAC_CTL_INT_EN 0x00000001 118 #define DWCDMAC_CTL_DST_TRWID(w) (((w) & 0x7) << 1) /* 2 = 32-bit */ 119 #define DWCDMAC_CTL_SRC_TRWID(w) (((w) & 0x7) << 4) 120 #define DWCDMAC_CTL_DINC_INC 0x00000000 121 #define DWCDMAC_CTL_DINC_DEC 0x00000080 122 #define DWCDMAC_CTL_DINC_NOCHANGE 0x00000100 123 #define DWCDMAC_CTL_SINC_INC 0x00000000 124 #define DWCDMAC_CTL_SINC_DEC 0x00000200 125 #define DWCDMAC_CTL_SINC_NOCHANGE 0x00000400 126 #define DWCDMAC_CTL_DST_MSIZE(m) (((m) & 0x7) << 11) /* 3 = 16 items */ 127 #define DWCDMAC_CTL_SRC_MSIZE(m) (((m) & 0x7) << 14) 128 #define DWCDMAC_CTL_TTFC(t) (((t) & 0x7) << 20) 129 #define DWCDMAC_TTFC_P2M_DMAC 0x2 /* dev->mem, DMAC flow control */ 130 #define DWCDMAC_TTFC_M2P_DMAC 0x1 /* mem->dev, DMAC flow control */ 131 #define DWCDMAC_TTFC_M2P_PER 0x3 /* mem->dev, periph flow control */ 132 #define DWCDMAC_CTL_DMS(m) (((m) & 0x3) << 23) /* dst master */ 133 #define DWCDMAC_CTL_SMS(m) (((m) & 0x3) << 25) /* src master */ 134 #define DWCDMAC_CTL_LLP_DST_EN 0x08000000 /* block chaining, dst */ 135 #define DWCDMAC_CTL_LLP_SRC_EN 0x10000000 /* block chaining, src */ 136 /* CTL, high word */ 137 #define DWCDMAC_CTL_BLOCK_TS(items) ((items) & 0xfff) 138 #define DWCDMAC_MAX_BLOCK_ITEMS 0x800 /* x4 bytes = 8KB per block */ 139 #define DWCDMAC_CTL_DONE 0x00001000 /* block done; written back to the 140 LLI ctl_hi in memory */ 141 142 /* CFG, low word */ 143 #define DWCDMAC_CFG_CH_PRIOR(p) (((p) & 0x7) << 5) 144 #define DWCDMAC_CFG_CH_SUSP 0x00000100 145 #define DWCDMAC_CFG_FIFO_EMPTY 0x00000200 146 #define DWCDMAC_CFG_HS_SEL_DST 0x00000400 /* 1 = software handshake */ 147 #define DWCDMAC_CFG_HS_SEL_SRC 0x00000800 148 /* CFG, high word */ 149 #define DWCDMAC_CFG_FCMODE_REQ 0x00000001 /* prefetch only on request */ 150 #define DWCDMAC_CFG_FIFO_MODE 0x00000002 /* burst only when FIFO ready */ 151 #define DWCDMAC_CFG_PROTCTL 0x0000000c /* AHB hprot, per Linux */ 152 #define DWCDMAC_CFG_HS_SRC(i) (((i) & 0xf) << 7) /* hw handshake if */ 153 #define DWCDMAC_CFG_HS_DST(i) (((i) & 0xf) << 11) 154 155 /* 156 * Master select encodes 157 */ 158 #define DWCDMAC_MS_PERIPH 0 159 #define DWCDMAC_MS_MEM 1 160 161 /* 162 * In-memory linked list item, fetched by the DMAC through the master 163 * named in the LMS bits. 164 */ 165 struct dwcdmac_lli { 166 uint32_t sar; 167 uint32_t dar; 168 uint32_t llp; /* phys addr of next item | LMS; 0 = last */ 169 uint32_t ctl_lo; 170 uint32_t ctl_hi; 171 uint32_t dstat_lo; 172 uint32_t dstat_hi; 173 }; 174 175 #endif /* _IBM4XX_DWCDMACREG_H_ */ 176
Indexes created Tue Jul 07 00:25:39 UTC 2026