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    Searched refs:DefI (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenPredicate.cpp 234 MachineInstr *DefI = MRI->getVRegDef(Reg.R);
235 DefI->eraseFromParent();
256 MachineInstr *DefI = MRI->getVRegDef(Reg.R);
257 assert(DefI);
258 unsigned Opc = DefI->getOpcode();
260 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
261 RegisterSubReg PR = DefI->getOperand(1);
267 MachineBasicBlock &B = *DefI->getParent();
268 DebugLoc DL = DefI->getDebugLoc()
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HexagonVExtract.cpp 149 MachineInstr *DefI = MRI.getVRegDef(VecR);
150 MachineBasicBlock::iterator At = std::next(DefI->getIterator());
151 MachineBasicBlock &DefB = *DefI->getParent();
155 Register AddrR = EmitAddr(DefB, At, DefI->getDebugLoc(), FI, 0);
156 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
HexagonExpandCondsets.cpp 343 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
344 if (HII->isPredicated(*DefI))
420 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
421 Defs.insert(DefI->getParent());
422 if (HII->isPredicated(*DefI))
474 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
475 for (auto &Op : DefI->operands()) {
491 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
492 if (!HII->isPredicated(*DefI))
498 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i)
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HexagonGenInsert.cpp 1025 const MachineInstr *DefI = MRI->getVRegDef(R);
1026 assert(DefI);
1030 if (DefI->isPHI())
1032 getInstrUses(DefI, Regs[OtherS]);
1161 const MachineInstr *DefI = MRI->getVRegDef(IR);
1164 unsigned DIV = distance(DefI, DefV, RPO, M);
1347 const MachineInstr *DefI = MRI->getVRegDef(I->first);
1348 getInstrUses(DefI, Us);
1445 MachineInstr *DefI = MRI->getVRegDef(I->first);
1447 DefI->eraseFromParent()
    [all...]
HexagonSplitDouble.cpp 235 MachineInstr *DefI = MRI->getVRegDef(R);
239 if (!DefI || isFixedInstr(DefI))
404 const MachineInstr *DefI = MRI->getVRegDef(Reg);
405 switch (DefI->getOpcode()) {
413 return profit(DefI);
426 MachineInstr *DefI = MRI->getVRegDef(DR);
427 int32_t P = profit(DefI);
1136 MachineInstr *DefI = MRI->getVRegDef(DR);
1137 SplitIns.insert(DefI);
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HexagonEarlyIfConv.cpp 408 const MachineInstr *DefI = MRI->getVRegDef(R);
410 assert(DefI && "Expecting a reaching def in MRI");
411 if (DefI->isImplicitDef())
HexagonConstExtenders.cpp 1504 const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr;
1508 assert(!DefI || MDT->dominates(DefI->getParent(), DomB));
HexagonBitSimplify.cpp 2298 MachineInstr *DefI = MRI.getVRegDef(Op0.getReg());
2299 assert(DefI != nullptr);
2300 if (!MDT.dominates(DefI, &*At))
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegStackify.cpp 317 const MachineInstr *DefI = Def->getParent();
319 assert(DefI->getParent() == Insert->getParent());
333 if (Def != DefI->defs().begin())
340 for (const auto &SubsequentDef : drop_begin(DefI->defs())) {
350 const MachineBasicBlock *MBB = DefI->getParent();
351 auto NextI = std::next(MachineBasicBlock::const_iterator(DefI));
359 if (WebAssembly::isCatch(DefI->getOpcode()))
364 for (const MachineOperand &MO : DefI->operands()) {
394 query(*DefI, AA, Read, Write, Effects, StackPointer);
402 // Scan through the intervening instructions between DefI and Insert
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MIRCanonicalizerPass.cpp 239 MachineBasicBlock::iterator DefI = BBE;
244 if (DefI != BBE && UseI != BBE)
248 DefI = BBI;
258 if (DefI == BBE || UseI == BBE)
263 DefI->dump();
270 MBB->splice(UseI, MBB, DefI);
MachineTraceMetrics.cpp 639 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
640 assert(!DefI.atEnd() && "Register has no defs");
641 DefMI = DefI->getParent();
642 DefOp = DefI.getOperandNo();
643 assert((++DefI).atEnd() && "Register has multiple defs");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUSubtarget.cpp 819 MachineInstr *DefI = Def->getInstr();
822 if (DefI->isBundle()) {
825 MachineBasicBlock::const_instr_iterator I(DefI->getIterator());
826 MachineBasicBlock::const_instr_iterator E(DefI->getParent()->instr_end());
840 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI);
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
LoopInfo.h 1188 auto *DefI = dyn_cast<Instruction>(U.get());
1189 if (!DefI)
1195 auto *DefBlock = DefI->getParent();
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
DeadStoreElimination.cpp 1737 Instruction *DefI = Def->getMemoryInst();
1739 auto DefLoc = getLocForWriteEx(DefI);
1756 deleteDeadInstruction(DefI);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
SimplifyIndVar.cpp 1157 auto *DefI = dyn_cast<Instruction>(Def);
1158 if (!DefI)
1161 assert(DT->dominates(DefI, InsertPt) && "def does not dominate all uses");
1163 auto *L = LI->getLoopFor(DefI->getParent());
1170 llvm_unreachable("DefI dominates InsertPt!");
  /src/external/apache2/llvm/dist/clang/utils/TableGen/
NeonEmitter.cpp 1403 DefInit *DefI = cast<DefInit>(DI->getOperator());
1404 std::string Op = DefI->getAsString();
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
Record.cpp 2158 if (DefInit *DefI = dyn_cast<DefInit>(Val))
2159 return DefI->getDef();

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