| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 181 /// instruction of itinerary class DefClass, operand index DefIdx can be
184 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
188 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
190 if (Forwardings[FirstDefIdx + DefIdx] == 0)
198 return Forwardings[FirstDefIdx + DefIdx] ==
205 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
210 int DefCycle = getOperandCycle(DefClass, DefIdx);
220 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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| MCSubtargetInfo.h | 176 unsigned DefIdx) const {
177 assert(DefIdx < SC->NumWriteLatencyEntries &&
178 "MachineModel does not specify a WriteResource for DefIdx");
180 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCSchedule.cpp | 43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
44 DefIdx != DefEnd; ++DefIdx) {
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx);
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 158 unsigned DefIdx = 0;
162 ++DefIdx;
164 return DefIdx;
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
222 STI->getWriteLatencyEntry(SCDesc, DefIdx);
238 // If DefIdx does not exist in the model (e.g. implicit defs), then return
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
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| LiveIntervalCalc.cpp | 45 SlotIndex DefIdx =
49 LR.createDeadDef(DefIdx, Alloc);
190 unsigned DefIdx;
193 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
196 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
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| TargetInstrInfo.cpp | 1090 SDNode *DefNode, unsigned DefIdx,
1100 return ItinData->getOperandCycle(DefClass, DefIdx);
1102 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1164 unsigned DefIdx) const {
1170 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1259 unsigned DefIdx,
1264 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1284 const MachineInstr &MI, unsigned DefIdx,
1290 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
1294 assert(DefIdx == 0 && "REG_SEQUENCE only has one def")
[all...] |
| PeepholeOptimizer.cpp | 373 unsigned DefIdx = 0;
427 DefIdx = MRI.def_begin(Reg).getOperandNo();
1818 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1839 const MachineOperand DefOp = Def->getOperand(DefIdx);
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1883 if (Def->getOperand(DefIdx).getSubReg())
1906 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1927 if (Def->getOperand(DefIdx).getSubReg())
1940 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1956 const MachineOperand &MODef = Def->getOperand(DefIdx);
[all...] |
| LiveRangeEdit.cpp | 149 SlotIndex DefIdx;
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
158 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| RenameIndependentSubregs.cpp | 335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
336 SlotIndex RegDefIdx = DefIdx.getRegSlot();
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| MachineInstr.cpp | 289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
895 unsigned DefIdx;
896 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
897 OpIdx = DefIdx;
1087 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1099 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1100 MachineOperand &DefMO = getOperand(DefIdx);
1102 assert(DefMO.isDef() && "DefIdx must be a def operand")
[all...] |
| MachineVerifier.cpp | 248 SlotIndex DefIdx, const LiveRange &LR,
1882 unsigned DefIdx;
1885 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1886 Reg != MI->getOperand(DefIdx).getReg())
2114 unsigned MONum, SlotIndex DefIdx,
2119 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2121 if (VNI->def != DefIdx) {
2128 report_context(DefIdx);
2136 report_context(DefIdx);
2140 LiveQueryResult LRQ = LR.Query(DefIdx);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 141 unsigned DefIdx;
160 return DefIdx-1;
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| ScheduleDAGSDNodes.cpp | 477 unsigned DefIdx = N->getOperand(i).getResNo();
512 ST.adjustSchedDependency(OpSU, DefIdx, SU, i, Dep);
575 DefIdx = 0;
581 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
589 for (;DefIdx < NodeNumDefs; ++DefIdx) {
590 if (!Node->hasAnyUseOfValue(DefIdx))
592 ValueType = Node->getSimpleValueType(DefIdx);
593 ++DefIdx;
655 unsigned DefIdx = Use->getOperand(OpIdx).getResNo()
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizationArtifactCombiner.h | 525 unsigned DefIdx = 0;
529 ++DefIdx;
532 return DefIdx;
629 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs;
630 ++j, ++DefIdx)
631 DstRegs.push_back(MI.getOperand(DefIdx).getReg());
682 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
684 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
219 DefIdx != DefEnd; ++DefIdx) {
222 DefIdx);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg());
406 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers))
573 int DefIdx = mapRegToGPRIndex(Def.getReg());
575 if (DefIdx >= 0 && OpIdx >= 0 &&
576 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx]))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 48 /// and \p DefIdx.
57 /// with the pair \p MI, \p DefIdx. False otherwise.
61 const MachineInstr &MI, unsigned DefIdx,
65 /// and \p DefIdx.
71 /// with the pair \p MI, \p DefIdx. False otherwise.
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
78 /// and \p DefIdx.
86 /// with the pair \p MI, \p DefIdx. False otherwise.
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
320 const MachineInstr &DefMI, unsigned DefIdx,
[all...] |
| ARMBaseInstrInfo.cpp | 3844 unsigned DefIdx, unsigned DefAlign) const {
3845 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3848 return ItinData->getOperandCycle(DefClass, DefIdx);
3885 unsigned DefIdx, unsigned DefAlign) const {
3886 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3889 return ItinData->getOperandCycle(DefClass, DefIdx);
3988 unsigned DefIdx, unsigned DefAlign,
3994 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3995 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4004 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetInstrInfo.h | 491 /// and \p DefIdx.
501 /// with the pair \p MI, \p DefIdx. False otherwise.
509 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
513 /// and \p DefIdx.
519 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
527 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
531 /// and \p DefIdx.
539 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
547 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1217 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 621 int DefIdx = SwapMap[DefMI];
622 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
626 SwapVector[DefIdx].VSEId,
725 int DefIdx = SwapMap[DefMI];
727 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
728 SwapVector[DefIdx].IsStore) {
734 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": ");
801 int DefIdx = SwapMap[DefMI];
802 SwapVector[DefIdx].WillRemove = 1
[all...] |
| PPCInstrInfo.h | 316 const MachineInstr &DefMI, unsigned DefIdx,
320 SDNode *DefNode, unsigned DefIdx,
322 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
328 unsigned DefIdx) const override {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 204 unsigned DefIdx = 0;
208 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
209 IsTiedToChangedOp = OpChanged[DefIdx];
295 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 495 int DefIdx = -1;
507 DefIdx = OpNum;
510 assert(DefIdx >= 0 && "Def Reg not found in Src MI");
517 DefIdx, *DstI, OpNum));
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InlineAsmLowering.cpp | 435 unsigned DefIdx = OpInfo.getMatchedOperand();
436 // Find operand with register def that corresponds to DefIdx.
438 for (unsigned i = 0; i < DefIdx; ++i)
472 unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
|
| Utils.cpp | 172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
173 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
174 I.tieOperands(DefIdx, OpI);
|
