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    Searched refs:DefInst (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFMISimplifyPatchable.cpp 108 MachineInstr *DefInst = I->getParent();
109 unsigned Opcode = DefInst->getOpcode();
123 const MachineOperand &ImmOp = DefInst->getOperand(2);
133 const MachineOperand &Opnd = DefInst->getOperand(0);
138 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp))
139 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp)
141 DefInst->eraseFromParent();
273 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCPreEmitPeephole.cpp 251 MachineBasicBlock::iterator DefInst;
313 MachineBasicBlock::iterator BBI = Pair->DefInst;
336 Pair->DefInst->addOperand(ImplDef);
344 Pair->DefInst->addOperand(*MF, PCRelLabel);
PPCBranchCoalescing.cpp 467 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg());
468 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) {
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
EarlyCSE.cpp 558 Instruction *DefInst = nullptr;
566 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId),
1107 if (InVal.DefInst == nullptr)
1122 Instruction *Matching = MemInstMatching ? MemInst.get() : InVal.DefInst;
1123 Instruction *Other = MemInstMatching ? InVal.DefInst : MemInst.get();
1130 if (MemInst.isStore() && InVal.DefInst != Result)
1139 if (!isNonTargetIntrinsicMatch(cast<IntrinsicInst>(InVal.DefInst),
1145 !isSameMemGeneration(InVal.Generation, CurrentGeneration, InVal.DefInst,
1410 << " to: " << *InVal.DefInst << '\n');
1491 if (InVal.DefInst &
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DeadStoreElimination.cpp 1106 /// (stored by \p DefInst).
1107 bool isCompleteOverwrite(const MemoryLocation &DefLoc, Instruction *DefInst,
1121 return isOverwrite(UseInst, DefInst, *CC, DefLoc, DepWriteOffset,
NewGVN.cpp 3928 auto *DefInst = dyn_cast_or_null<Instruction>(Def);
3929 if (DefInst && AllTempInstructions.count(DefInst)) {
3930 auto *PN = cast<PHINode>(DefInst);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCopyToCombine.cpp 416 MachineInstr *DefInst = LastDef[Reg];
417 if (!DefInst)
419 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
424 MachineBasicBlock::iterator It(DefInst);
435 PotentiallyNewifiableTFR.insert(DefInst);
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
MemorySSA.cpp 272 Instruction *DefInst = MD->getMemoryInst();
273 assert(DefInst && "Defining instruction not actually an instruction");
276 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) {
301 ModRefInfo I = AA.getModRefInfo(DefInst, CB);
306 if (auto *DefLoad = dyn_cast<LoadInst>(DefInst))
311 ModRefInfo I = AA.getModRefInfo(DefInst, UseLoc);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPeepholeSDWA.cpp 504 const MachineInstr *DefInst = Def.getParent();
505 if (!TII->isFoldableCopy(*DefInst))
508 const MachineOperand &Copied = DefInst->getOperand(1);
SIInstrInfo.cpp 7627 auto *DefInst = MRI.getVRegDef(RSR.Reg);
7628 while (auto *MI = DefInst) {
7629 DefInst = nullptr;
7638 DefInst = MRI.getVRegDef(RSR.Reg);
7646 DefInst = MRI.getVRegDef(RSR.Reg);
7649 if (!DefInst)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocFast.cpp 392 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
393 if (DefInst.getParent() != MBB || ++C >= Limit) {

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