| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
96 if (DefMI->getParent() != MBB)
98 if (DefMI->isCopyLike()) {
99 Reg = DefMI->getOperand(1).getReg();
101 DefMI = MRI->getVRegDef(Reg);
104 } else if (DefMI->isInsertSubreg()) {
105 Reg = DefMI->getOperand(2).getReg();
107 DefMI = MRI->getVRegDef(Reg);
113 return DefMI;
146 MachineInstr *DefMI = MRI->getVRegDef(Reg)
[all...] |
| ARMHazardRecognizer.cpp | 26 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
37 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
52 MachineInstr *DefMI = LastMI;
65 DefMI = &*I;
69 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
71 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 185 const MachineInstr *DefMI, unsigned DefOperIdx,
189 return TII->defaultDefLatency(SchedModel, *DefMI);
194 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
198 unsigned DefClass = DefMI->getDesc().getSchedClass();
205 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
213 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
217 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
241 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef(
[all...] |
| LiveRangeEdit.cpp | 71 const MachineInstr *DefMI,
73 assert(DefMI && "Missing instruction");
75 if (!TII.isTriviallyReMaterializable(*DefMI, aa))
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
91 if (!DefMI)
93 checkRematerializable(OrigVNI, DefMI, aa);
187 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
193 if (DefMI && DefMI != MI)
197 DefMI = MI
[all...] |
| MachineTraceMetrics.cpp | 628 const MachineInstr *DefMI;
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
641 DefMI = DefI->getParent();
770 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
772 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()];
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
795 BlockInfo[Dep.DefMI->getParent()->getNumber()];
800 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth
[all...] |
| PHIElimination.cpp | 166 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
167 if (!DefMI)
178 MachineBasicBlock *DefMBB = DefMI->getParent();
202 for (MachineInstr *DefMI : ImpDefs) {
203 Register DefReg = DefMI->getOperand(0).getReg();
206 LIS->RemoveMachineInstrFromMaps(*DefMI);
207 DefMI->eraseFromParent();
474 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
475 if (DefMI->isImplicitDef())
476 ImpDefs.insert(DefMI);
[all...] |
| RegisterCoalescer.cpp | 827 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
828 if (!DefMI)
830 if (!DefMI->isCommutable())
832 // If DefMI is a two-address instruction then commuting it will change the
834 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg());
837 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
850 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
853 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
878 << *DefMI);
882 MachineBasicBlock *MBB = DefMI->getParent()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64CondBrTuning.cpp | 66 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
143 MachineInstr &DefMI) {
145 if (MI.getParent() != DefMI.getParent())
151 switch (DefMI.getOpcode()) {
195 // There must not be any instruction between DefMI and MI that clobbers or
197 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI))
200 LLVM_DEBUG(DefMI.print(dbgs()));
204 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
250 // There must not be any instruction between DefMI and MI that clobbers or
252 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TileConfig.cpp | 155 for (auto &DefMI : MRI.def_instructions(R)) {
156 MachineBasicBlock &MBB = *DefMI.getParent();
157 if (DefMI.isMoveImmediate()) {
160 assert(Imm == DefMI.getOperand(1).getImm() &&
164 Imm = DefMI.getOperand(1).getImm();
177 auto Iter = DefMI.getIterator();
|
| X86OptimizeLEAs.cpp | 352 for (auto DefMI : List) {
354 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1);
366 MRI->getRegClass(DefMI->getOperand(0).getReg()))
373 int DistTemp = calcInstrDist(*DefMI, MI);
383 BestLEA = DefMI;
529 MachineInstr *DefMI;
532 if (!chooseBestLEA(Insns->second, MI, DefMI, AddrDispShift, Dist))
542 DefMI->removeFromParent();
543 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI);
544 InstrPos[DefMI] = InstrPos[&MI] - 1
[all...] |
| X86PreTileConfig.cpp | 211 MachineInstr *DefMI = MRI->getVRegDef(R);
212 assert(DefMI && "R must has one define instruction");
213 MachineBasicBlock *DefMBB = DefMI->getParent();
214 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second)
216 if (DefMI->isPHI()) {
217 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2)
218 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB()))
219 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def.
221 WorkList.push_back(DefMI->getOperand(I).getReg())
[all...] |
| X86CallFrameOptimization.cpp | 620 MachineInstr &DefMI = *MRI->getVRegDef(Reg);
624 if ((DefMI.getOpcode() != X86::MOV32rm &&
625 DefMI.getOpcode() != X86::MOV64rm) ||
626 DefMI.getParent() != FrameSetup->getParent())
629 // Make sure we don't have any instructions between DefMI and the
631 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I)
635 return &DefMI;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 280 MachineInstr *DefMI = MRI.getVRegDef(Reg);
282 assert(DefMI);
284 // See if DefMI is an instruction that loads from a GOT entry that holds the
286 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
289 unsigned Flags = DefMI->getOperand(2).getTargetFlags();
295 assert(DefMI->hasOneMemOperand());
296 Val = (*DefMI->memoperands_begin())->getValue();
298 Val = (*DefMI->memoperands_begin())->getPseudoValue();
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| Utils.cpp | 387 auto *DefMI = MRI.getVRegDef(Reg);
388 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
391 unsigned Opc = DefMI->getOpcode();
393 Register SrcReg = DefMI->getOperand(1).getReg();
397 DefMI = MRI.getVRegDef(SrcReg);
399 Opc = DefMI->getOpcode();
401 return DefinitionAndSourceRegister{DefMI, DefSrcReg};
420 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI);
421 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 174 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
198 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFMIPeephole.cpp | 464 MachineInstr *DefMI;
491 DefMI = MRI->getVRegDef(SrcReg);
492 if (DefMI)
498 DefMI = MRI->getVRegDef(SrcReg);
500 if (!DefMI)
514 if (DefMI->isPHI()) {
517 for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) {
518 MachineOperand &opnd = DefMI->getOperand(i);
534 } else if (!TruncSizeCompatible(TruncSize, DefMI->getOpcode())) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 202 // Replace the instruction with single LI if possible. \p DefMI must be LI or
204 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
208 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
214 MachineInstr &DefMI) const;
218 unsigned ConstantOpNo, MachineInstr &DefMI,
233 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
238 const MachineInstr &DefMI,
243 const MachineInstr &DefMI,
316 const MachineInstr &DefMI, unsigned DefIdx,
327 const MachineInstr &DefMI,
[all...] |
| PPCMIPeephole.cpp | 518 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
520 if (!DefMI)
523 unsigned DefOpc = DefMI->getOpcode();
533 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
556 unsigned DefReg1 = DefMI->getOperand(1).getReg();
557 unsigned DefReg2 = DefMI->getOperand(2).getReg();
558 unsigned DefImmed = DefMI->getOperand(3).getImm();
602 .add(DefMI->getOperand(1));
607 (DefMI->getOperand(2).getImm() == 0 ||
608 DefMI->getOperand(2).getImm() == 3))
[all...] |
| PPCVSXSwapRemoval.cpp | 618 MachineInstr* DefMI = MRI->getVRegDef(Reg);
619 assert(SwapMap.find(DefMI) != SwapMap.end() &&
621 int DefIdx = SwapMap[DefMI];
629 LLVM_DEBUG(DefMI->dump());
723 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
724 Register DefReg = DefMI->getOperand(0).getReg();
725 int DefIdx = SwapMap[DefMI];
735 LLVM_DEBUG(DefMI->dump());
741 // Ensure all uses of the register defined by DefMI feed store
754 LLVM_DEBUG(DefMI->dump())
[all...] |
| PPCInstrInfo.cpp | 167 const MachineInstr &DefMI, unsigned DefIdx,
170 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
173 if (!DefMI.getParent())
176 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
182 &DefMI.getParent()->getParent()->getRegInfo();
192 Latency = getInstrLatency(ItinData, DefMI);
751 MachineInstr *DefMI = MRI->getVRegDef(Reg);
752 for (auto MO2 : DefMI->uses())
2040 bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2043 unsigned DefOpc = DefMI.getOpcode()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.h | 105 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
|
| VEInstrInfo.cpp | 546 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
550 LLVM_DEBUG(dbgs() << "checking DefMI\n");
552 switch (DefMI.getOpcode()) {
558 LLVM_DEBUG(DefMI.dump());
560 assert(DefMI.getOperand(1).isImm());
561 assert(DefMI.getOperand(2).isImm());
563 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm());
569 LLVM_DEBUG(DefMI.dump());
571 assert(DefMI.getOperand(2).isImm())
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizationArtifactCombiner.h | 324 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
347 markInstAndDefDead(MI, *DefMI, DeadInsts);
905 /// Mark a def of one of MI's original operands, DefMI, as dead if changing MI
906 /// (either by killing it or changing operands) results in DefMI being dead
910 void markDefDead(MachineInstr &MI, MachineInstr &DefMI,
914 // this instruction. Collect all of them until the Trunc(DefMI).
923 while (PrevMI != &DefMI) {
928 if (TmpDef != &DefMI) {
940 if (PrevMI == &DefMI) {
943 for (MachineOperand &Def : DefMI.defs())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 625 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
630 if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) {
736 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg());
737 if (DefMI && TII->isFoldableCopy(*DefMI)) {
738 const MachineOperand &Def = DefMI->getOperand(0);
742 const MachineOperand &Copied = DefMI->getOperand(1);
827 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg());
828 if (DefMI && DefMI->isPHI()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
499 bool Invert = !DefMI;
500 if (!DefMI)
501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
502 if (!DefMI)
512 // Create a new predicated version of DefMI.
514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
516 // Copy all the DefMI operands, excluding its (null) predicate.
517 const MCInstrDesc &DefDesc = DefMI->getDesc();
520 NewMI.add(DefMI->getOperand(i))
[all...] |
