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    Searched refs:DefOp (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineTraceMetrics.cpp 629 unsigned DefOp;
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
642 DefOp = DefI.getOperandNo();
740 for (unsigned DefOp : LiveDefOps) {
741 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg().asMCReg(),
746 LRU.Op = DefOp;
804 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
959 UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI
    [all...]
PeepholeOptimizer.cpp 1519 MachineOperand &DefOp = MI.getOperand(0);
1520 if (!isVirtualRegisterOperand(DefOp))
1532 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1538 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1839 const MachineOperand DefOp = Def->getOperand(DefIdx);
1840 if (DefOp.getSubReg() != DefSubReg)
1868 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
SplitKit.cpp 449 for (const MachineOperand &DefOp : DefMI->defs()) {
450 Register R = DefOp.getReg();
453 if (unsigned SR = DefOp.getSubReg())
MachinePipeliner.cpp 390 MachineOperand &DefOp = PI.getOperand(0);
391 assert(DefOp.getSubReg() == 0);
392 auto *RC = MRI.getRegClass(DefOp.getReg());
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineTraceMetrics.h 335 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SpeculativeLoadHardening.cpp 1207 if (const MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) {
1208 return !DefOp->isDead();
1218 if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) {
1220 if (DefOp->isDead())
1965 auto &DefOp = MI.getOperand(0);
1966 Register OldDefReg = DefOp.getReg();
1973 DefOp.setReg(UnhardenedReg);
X86DomainReassignment.cpp 588 for (auto &DefOp : UseMI.defs()) {
589 if (!DefOp.isReg())
592 Register DefReg = DefOp.getReg();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 226 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
855 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
886 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 568 MachineOperand &DefOp = Def->getOperand(1);
569 if (DefOp.isImm() && TII->isInlineConstant(DefOp, OpTy) &&
570 TII->isOperandLegal(*UseMI, UseOpIdx, &DefOp)) {
571 UseMI->getOperand(UseOpIdx).ChangeToImmediate(DefOp.getImm());
SIInstrInfo.cpp 519 MachineOperand &DefOp = Def->getOperand(1);
520 assert(DefOp.isReg() || DefOp.isImm());
522 if (DefOp.isReg()) {
527 if (I->modifiesRegister(DefOp.getReg(), &RI))
533 DefOp.setIsKill(false);
538 .add(DefOp);

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