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    Searched refs:DefR (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonConstPropagation.cpp 634 RegisterSubReg DefR(MD);
635 assert(DefR.Reg.isVirtual());
640 if (DefR.SubReg) {
642 const LatticeCell &T = Cells.get(DefR.Reg);
644 Cells.update(DefR.Reg, Bottom);
646 visitUsesOf(DefR.Reg);
650 LatticeCell DefC = Cells.get(DefR.Reg);
677 Cells.update(DefR.Reg, DefC);
682 visitUsesOf(DefR.Reg);
704 RegisterSubReg DefR(MO)
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HexagonGenMux.cpp 108 unsigned DefR, PredR;
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
343 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
HexagonEarlyIfConv.cpp 441 Register DefR = MI.getOperand(0).getReg();
442 if (isPredicate(DefR))
993 Register DefR = PN->getOperand(0).getReg();
1000 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
1005 MRI->replaceRegWith(DefR, NewR);
HexagonConstExtenders.cpp 1528 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1541 // DefR = PS_fi Rb,##EV
1542 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR)
1548 // DefR = ##EV
1549 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR)
1553 // DefR = sub(##EV,Rb)
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1558 // DefR = add(Rb,##EV)
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1567 // DefR = add(##EV,asl(Rb,S)
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HexagonOptAddrMode.cpp 97 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
729 Register DefR = MI->getOperand(0).getReg();
734 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc))
758 if (op.isReg() && op.isUse() && DefR == op.getReg())
762 // This could happen, for example, when DefR = R4, but the used
HexagonBitSimplify.cpp 1222 Register DefR = UseI.getOperand(0).getReg();
1223 if (!DefR.isVirtual())
1225 Pending.push_back(DefR);
2929 unsigned DefR;
2936 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2937 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2955 DefR = HexagonLoopRescheduling::getDefReg(&P);
2990 unsigned DefR) const {
3144 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
3172 Register DefR = Defs.find_first()
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HexagonBitTracker.cpp 961 if (unsigned DefR = getUniqueDefVReg(MI)) {
962 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
963 BT::RegisterRef PD(DefR, 0);
966 RegisterCell RC = RegisterCell::self(DefR, RW);

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