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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
DetectDeadLanes.cpp 250 Register DefReg = Def.getReg();
251 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
285 Register DefReg = Def.getReg();
286 if (!Register::isVirtualRegister(DefReg))
288 unsigned DefRegIdx = Register::virtReg2Index(DefReg);
428 Register DefReg = Def.getReg();
431 if (Register::isVirtualRegister(DefReg)) {
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
470 Register DefReg = Def.getReg();
471 if (!Register::isVirtualRegister(DefReg))
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TailDuplicator.cpp 352 Register DefReg = MI->getOperand(0).getReg();
357 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
358 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg)));
364 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
365 addSSAUpdateEntry(DefReg, NewDef, PredBB);
ImplicitNullChecks.cpp 718 unsigned DefReg = NoRegister;
720 DefReg = MI->getOperand(0).getReg();
731 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
PHIElimination.cpp 203 Register DefReg = DefMI->getOperand(0).getReg();
204 if (MRI->use_nodbg_empty(DefReg)) {
MachineSink.cpp 1606 for (auto DefReg : DefedRegsInCopy) {
1608 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI);
1641 for (unsigned DefReg : DefedRegsInCopy)
1642 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
1779 "Unexpect SrcReg or DefReg");
TargetInstrInfo.cpp 926 Register DefReg = MI.getOperand(0).getReg();
932 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
933 MI.readsVirtualRegister(DefReg))
984 if (MO.isDef() && Reg != DefReg)
LiveVariables.cpp 216 Register DefReg = MO.getReg();
217 if (TRI->isSubRegister(Reg, DefReg)) {
218 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64RedundantCopyElimination.cpp 382 Register DefReg = MI->getOperand(0).getReg();
385 if (!MRI->isReserved(DefReg) &&
389 if (KnownReg.Reg != DefReg &&
390 !TRI->isSuperRegister(DefReg, KnownReg.Reg))
414 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0)
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegStackify.cpp 469 Register DefReg = MO.getReg();
470 if (!Register::isVirtualRegister(DefReg) ||
471 !MFI.isVRegStackified(DefReg))
473 assert(MRI.hasOneNonDBGUse(DefReg));
474 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg);
618 /// DefReg = INST ... // Def (to become the new Insert)
619 /// TeeReg, Reg = TEE_... DefReg
624 /// with DefReg and TeeReg stackified. This eliminates a local.get from the
641 Register DefReg = MRI.createVirtualRegister(RegClass);
646 .addReg(DefReg, getUndefRegState(DefMO.isDead()))
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WebAssemblyExplicitLocals.cpp 192 for (auto DefReg : Def->defs()) {
193 if (!MFI.isVRegStackified(DefReg.getReg())) {
WebAssemblyCFGStackify.cpp 829 // DefReg = INST ...
830 // TeeReg, Reg = TEE_... DefReg
834 // with DefReg and TeeReg stackified but Reg not stackified.
839 // DefReg = INST ...
840 // TeeReg = COPY DefReg
841 // Reg = COPY DefReg
851 Register DefReg = MI.getOperand(2).getReg();
853 // Now we are not using TEE anymore, so unstackify DefReg too
854 MFI.unstackifyVReg(DefReg);
855 unsigned CopyOpc = getCopyOpcode(MRI.getRegClass(DefReg));
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 397 Register DefReg = MI.getOperand(I).getReg();
398 UpdatedDefs.push_back(DefReg);
399 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I));
688 Register DefReg = MI.getOperand(DefIdx).getReg();
689 Builder.buildMerge(DefReg, Regs);
690 UpdatedDefs.push_back(DefReg);
704 Register DefReg = MI.getOperand(Idx).getReg();
705 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc});
706 UpdatedDefs.push_back(DefReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCPreEmitPeephole.cpp 253 Register DefReg;
285 if (!BBI->readsRegister(Pair.DefReg, TRI) &&
286 !BBI->modifiesRegister(Pair.DefReg, TRI))
295 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg &&
PPCVSXSwapRemoval.cpp 671 Register DefReg = MI->getOperand(0).getReg();
677 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
724 Register DefReg = DefMI->getOperand(0).getReg();
743 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
783 Register DefReg = MI->getOperand(0).getReg();
785 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 508 const Register DefReg = I.getOperand(0).getReg();
509 LLT Ty = MRI.getType(DefReg);
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
546 addFullAddress(MIB, AM).addUse(DefReg);
568 const Register DefReg = I.getOperand(0).getReg();
569 LLT Ty = MRI.getType(DefReg);
621 const Register DefReg = I.getOperand(0).getReg();
622 LLT Ty = MRI.getType(DefReg);
640 const Register DefReg = I.getOperand(0).getReg();
641 LLT Ty = MRI.getType(DefReg);
    [all...]
X86DomainReassignment.cpp 592 Register DefReg = DefOp.getReg();
593 if (!DefReg.isVirtual()) {
597 visitRegister(C, DefReg, Domain, Worklist);
X86LoadValueInjectionLoadHardening.cpp 370 RegisterRef DefReg = Def.Addr->getRegRef(DFG);
371 for (auto UseID : L.getAllReachedUses(DefReg, Def)) {
376 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) {
X86SpeculativeLoadHardening.cpp 1786 Register DefReg = MI.getOperand(0).getReg();
1792 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) {
1817 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) ||
1818 (IndexMO.isReg() && IndexMO.getReg() == DefReg))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
Mips16InstrInfo.cpp 369 int DefReg = 0;
373 DefReg = MO.getReg();
392 if (DefReg != Reg) {
407 if (DefReg!= SpReg) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 248 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS,
269 /// \p DefReg and \p SrcReg are expected to be 32-bit scalar registers.
270 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
2109 Register DefReg = I.getOperand(0).getReg();
2110 LLT Ty = MRI.getType(DefReg);
2113 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
2116 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
2189 const Register DefReg = I.getOperand(0).getReg();
2190 const LLT DefTy = MRI.getType(DefReg);
2193 MRI.getRegClassOrRegBank(DefReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
A15SDOptimizer.cpp 215 Register DefReg = MODef.getReg();
216 if (!Register::isVirtualRegister(DefReg)) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 178 static bool isRegUsedByPhiNodes(Register DefReg,
181 if (P.second == DefReg)
202 Register DefReg = findLocalRegDef(LocalMI);
203 if (!DefReg)
205 if (FuncInfo.RegsWithFixups.count(DefReg))
207 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
208 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 1658 Register DefReg = Def.getReg();
1660 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg))
1665 for (const MachineInstr &I : MRI->use_nodbg_instructions(DefReg)) {
1685 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
1686 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC));
1688 MRI->setRegClass(DefReg, RC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.cpp 1039 unsigned DefReg = 0;
1046 if (DefReg != 0)
1048 DefReg = R;
1050 return DefReg;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegBankSelect.cpp 204 for (Register DefReg : NewVRegs)
205 UnMergeBuilder.addDef(DefReg);

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