| /src/external/apache2/llvm/dist/clang/utils/TableGen/ |
| ClangDataCollectorsEmitter.cpp | 8 const auto &Defs = RK.getClasses();
9 for (const auto &Entry : Defs) {
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| RISCVVEmitter.cpp | 238 /// Emit Acrh predecessor definitions and body, assume the element of Defs are
241 std::vector<std::unique_ptr<RVVIntrinsic>> &Defs, raw_ostream &o,
901 std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
902 createRVVIntrinsics(Defs);
957 std::stable_sort(Defs.begin(), Defs.end(),
964 emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
974 emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
988 std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
989 createRVVIntrinsics(Defs);
[all...] |
| NeonEmitter.cpp | 548 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
550 SmallVectorImpl<Intrinsic *> &Defs);
552 SmallVectorImpl<Intrinsic *> &Defs);
1994 SmallVectorImpl<Intrinsic *> &Defs) {
2001 for (auto *Def : Defs) {
2021 SmallVectorImpl<Intrinsic *> &Defs) {
2035 for (auto *Def : Defs) {
2100 SmallVectorImpl<Intrinsic *> &Defs) {
2105 for (auto *Def : Defs) {
2190 SmallVector<Intrinsic *, 128> Defs;
[all...] |
| SveEmitter.cpp | 1230 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
1233 createIntrinsic(R, Defs);
1240 Defs.begin(), Defs.end(), [](const std::unique_ptr<Intrinsic> &A,
1249 for (auto &I : Defs) {
1291 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
1293 createIntrinsic(R, Defs);
1296 llvm::sort(Defs, [](const std::unique_ptr<Intrinsic> &A,
1302 for (auto &Def : Defs) {
1322 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
106 InsertUsesDefs(LocalDefs, Defs);
138 RegisterSet &Defs, RegisterSet &Uses) {
152 if (Uses.count(DstReg) || Defs.count(SrcReg))
196 RegisterSet Defs, Uses;
209 Defs.clear();
211 TrackDefUses(MI, Defs, Uses, TRI);
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
262 TrackDefUses(NMI, Defs, Uses, TRI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPostRABundler.cpp | 49 SmallSet<Register, 16> Defs;
83 for (Register Def : Defs)
140 assert(Defs.empty());
143 Defs.insert(I->defs().begin()->getReg());
155 Defs.insert(I->defs().begin()->getReg());
208 Defs.clear();
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| SIFormMemoryClauses.cpp | 63 bool canBundle(const MachineInstr &MI, const RegUse &Defs,
66 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
120 for (const MachineOperand &ResMO : MI.defs()) {
152 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs,
154 // Check interference with defs.
170 const RegUse &Map = MO.isDef() ? Uses : Defs;
186 // Since all defs in the clause are early clobber we can run out of registers.
191 // NB: skip advanceBeforeNext() call. Since all defs will be marked
217 // Collect register defs and uses along with their lane masks and states
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CTagsEmitter.cpp | 66 const auto &Defs = Records.getDefs();
69 Tags.reserve(Classes.size() + Defs.size());
72 for (const auto &D : Defs)
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCBoolRetToInt.cpp | 73 SmallPtrSet<Value *, 8> Defs;
76 Defs.insert(V);
84 if (Defs.insert(Op).second)
87 return Defs;
222 auto Defs = findAllDefs(U);
225 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); }))
231 for (Value *V : Defs)
236 for (Value *V : Defs)
247 for (Value *V : Defs)
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenMux.cpp | 100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
160 // First, get the implicit defs and uses for this instruction.
165 expandReg(*R++, Defs);
170 // Look over all operands, and collect explicit defs and uses.
175 BitVector &Set = MO.isDef() ? Defs : Uses;
184 BitVector Defs(NR), Uses(NR);
189 Defs.reset()
[all...] |
| HexagonRDFOpt.cpp | 256 NodeList Defs;
261 Defs = DFG.getRelatedRefs(IA, DA);
262 if (!llvm::all_of(Defs, IsDead))
267 // Mark all nodes in Defs for removal.
268 for (auto D : Defs)
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| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| MemorySSAUpdater.cpp | 155 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock());
157 // It's possible there are no defs, or we got handed the first def to start.
158 if (Defs) {
163 if (Iter != Defs->rend())
171 // Note that if MA comes before Defs->begin(), we won't hit a def.
182 auto *Defs = MSSA->getWritableBlockDefs(BB);
184 if (Defs) {
185 CachedPreviousDef.insert({BB, &*Defs->rbegin()});
186 return &*Defs->rbegin();
250 // may-defs, there are only two cases
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| ReachingDefAnalysis.cpp | 244 // Make sure reaching defs are sorted and unique.
249 assert(Def > LastDef && "Defs must be sorted and unique");
397 InstSet &Defs) const {
399 Defs.insert(Def);
404 getLiveOuts(MBB, PhysReg, Defs);
408 MCRegister PhysReg, InstSet &Defs) const {
410 getLiveOuts(MBB, PhysReg, Defs, VisitedBBs);
414 MCRegister PhysReg, InstSet &Defs,
426 Defs.insert(Def);
429 getLiveOuts(Pred, PhysReg, Defs, VisitedBBs)
[all...] |
| LiveVariables.cpp | 227 /// implicit defs to a machine instruction if there was an earlier def of its
442 SmallVectorImpl<unsigned> &Defs) {
481 Defs.push_back(Reg); // Remember this def.
485 SmallVectorImpl<unsigned> &Defs) {
486 while (!Defs.empty()) {
487 Register Reg = Defs.back();
488 Defs.pop_back();
499 SmallVectorImpl<unsigned> &Defs) {
551 // Process all defs.
557 HandlePhysRegDef(MOReg, &MI, Defs);
[all...] |
| MachineInstrBundle.cpp | 121 /// bundle, and it copies externally visible defs and uses to the BUNDLE
145 SmallVector<MachineOperand*, 4> Defs;
152 Defs.push_back(&MO);
177 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
178 MachineOperand &MO = *Defs[i];
205 Defs.clear();
291 // Both defs and uses can read virtual registers.
298 // Only defs can write.
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| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| Instruction.h | 406 SmallVector<WriteState, 4> Defs;
415 SmallVectorImpl<WriteState> &getDefs() { return Defs; }
416 ArrayRef<WriteState> getDefs() const { return Defs; }
425 return any_of(Defs,
431 for (const WriteState &Def : Defs)
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
45 Defs[Hexagon::LC0].insert(Unconditional);
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
49 Defs[Hexagon::LC1].insert(Unconditional);
127 Defs[R].insert(PredSense(PredReg, isTrue));
134 // reset R to USR, since we know how to handle multiple defs of USR,
182 Defs[*SRI].insert(PredSense(PredReg, isTrue));
394 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) {
407 if (LatePreds.count(P) > 1 || Defs.count(P))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 115 /// This function sets all caller-saved registers in Defs.
118 /// This function sets all unallocatable registers in Defs.
136 BitVector Defs, Uses;
192 /// Update Defs and Uses. Return true if there exist dependences that
194 /// Defs.
202 SmallPtrSet<ValueType, 4> Uses, Defs;
345 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
351 // If MI is a call, add RA to Defs to prevent users of RA from going into
354 Defs.set(Mips::RA);
360 Defs.reset(Mips::AT)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| RDFLiveness.h | 103 NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs);
165 NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs,
|
| LiveVariables.h | 158 SmallVectorImpl<unsigned> &Defs);
159 void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
177 void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
|
| ReachingDefAnalysis.h | 9 /// \file Reaching Defs Analysis pass.
96 /// All reaching defs of a given RegUnit for a given MBB.
98 /// All reaching defs of all reg units for a given MBB
100 /// All reaching defs of all reg units for a all MBBs
190 /// Search MBB for a definition of PhysReg and insert it into Defs. If no
192 void getLiveOuts(MachineBasicBlock *MBB, MCRegister PhysReg, InstSet &Defs,
195 InstSet &Defs) const;
210 InstSet &Defs) const;
256 /// Also break dependencies on partial defs and undef uses.
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ExecutionEngine/Orc/ |
| CompileOnDemandLayer.h | 124 IRMaterializationUnit::SymbolNameToDefinitionMap Defs);
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| ParallelSnippetGenerator.cpp | 188 // No tied variables, we pick random values for defs.
189 BitVector Defs(State.getRegInfo().getNumRegs());
197 Defs.set(RandomReg);
201 // And pick random use values that are not reserved and don't alias with defs.
202 const auto DefAliases = getAliasedBits(State.getRegInfo(), Defs);
214 "instruction has no tied variables picking Uses different from defs";
|
| MCInstrDescView.cpp | 31 // TiedOperands[0] is the Def operand (LLVM stores defs first).
322 return std::tie(Defs, Uses) == std::tie(Other.Defs, Other.Uses);
342 return any_of(Defs, HasImplicit) && any_of(Uses, HasImplicit);
360 addOperandIfAlias(Reg, true, DefInstruction.Operands, ARO.Defs);
362 if (!ARO.Defs.empty() && !ARO.Uses.empty() &&
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| /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/Orc/ |
| CompileOnDemandLayer.cpp | 260 IRMaterializationUnit::SymbolNameToDefinitionMap Defs) {
276 assert(Defs.count(Name) && "No definition for symbol");
277 RequestedGVs.insert(Defs[Name]);
290 Defs.clear();
300 std::move(Defs), *this))) {
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