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    Searched refs:DesiredReg (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp 1593 Register DesiredReg = MI.getOperand(3).getReg();
1601 assert(ARM::tGPRRegClass.contains(DesiredReg) &&
1602 "DesiredReg used for UXT op must be tGPR");
1616 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
1617 .addReg(DesiredReg, RegState::Kill);
1638 .addReg(DesiredReg)
1721 Register DesiredReg = MI.getOperand(3).getReg();
1727 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1728 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandPseudoInsts.cpp 197 Register DesiredReg = MI.getOperand(3).getReg();
221 .addReg(DesiredReg)
AArch64FastISel.cpp 4983 const unsigned DesiredReg = constrainOperandRegClass(
4997 .addUse(DesiredReg)
5003 .addUse(DesiredReg)

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