HomeSort by: relevance | last modified time | path
    Searched refs:DestSub0 (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 1698 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1701 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0)
1722 .addReg(DestSub0)
SIInstrInfo.cpp 6349 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
6350 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
6359 std::swap(DestSub0, DestSub1);
6363 .addReg(DestSub0)
6390 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6420 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
6436 .addReg(DestSub0)
6490 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
6491 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
6502 .addReg(DestSub0)
    [all...]
SIISelLowering.cpp 3917 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3934 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
3937 .addReg(DestSub0)
3955 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3988 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
4004 .addReg(DestSub0)

Completed in 54 milliseconds