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    Searched refs:DestSub1 (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 1699 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1710 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1)
1724 .addReg(DestSub1)
SIInstrInfo.cpp 6355 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
6356 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
6359 std::swap(DestSub0, DestSub1);
6365 .addReg(DestSub1)
6391 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6428 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
6438 .addReg(DestSub1)
6495 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
6496 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
6504 .addReg(DestSub1)
    [all...]
SIISelLowering.cpp 3918 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3935 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1);
3939 .addReg(DestSub1)
3956 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3996 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
4006 .addReg(DestSub1)

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