| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 233 MVT::SimpleValueType DestVT = getValueType(DestTy);
234 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n";
235 if (MVT(DestVT).isFloatingPoint()) {
247 MVT::SimpleValueType DestVT = getValueType(DestTy);
248 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n";
249 if (MVT(DestVT).isFloatingPoint()) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
998 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1000 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1077 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1079 if (SrcVT != MVT::f64 || DestVT != MVT::f32
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 168 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
958 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
976 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
978 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1268 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1272 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1440 MVT DestVT = VA.getLocVT();
1442 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass
[all...] |
| PPCISelLowering.h | 971 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
|
| PPCISelLowering.cpp | 8860 const SDLoc &dl, EVT DestVT = MVT::Other) {
8861 if (DestVT == MVT::Other) DestVT = Op.getValueType();
8862 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
8870 EVT DestVT = MVT::Other) {
8871 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
8872 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
8880 EVT DestVT = MVT::Other) {
8881 if (DestVT == MVT::Other) DestVT = Op0.getValueType()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 231 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
232 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2804 MVT DestVT;
2805 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2819 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2821 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2824 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2826 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2829 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass)
[all...] |
| AArch64ISelLowering.cpp | 8282 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
8289 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
8309 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8315 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8320 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8323 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8334 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
16361 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
16364 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 201 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1734 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1738 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1949 MVT DestVT = VA.getLocVT();
1950 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1952 ArgVT = DestVT;
1958 MVT DestVT = VA.getLocVT();
1959 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true)
[all...] |
| ARMISelLowering.cpp | 7810 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
7818 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
7834 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7840 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7845 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7848 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7851 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 157 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
876 EVT DestVT = Node->getValueType(0);
877 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
903 EVT IDestVT = DestVT.changeTypeToInteger();
908 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1686 /// a load from the stack slot to DestVT, extending it if needed.
1689 EVT DestVT, const SDLoc &dl) {
1690 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1694 EVT DestVT, const SDLoc &dl
[all...] |
| LegalizeTypes.cpp | 887 EVT DestVT) {
894 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false);
903 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align);
|
| SelectionDAGBuilder.cpp | 3207 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3209 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3230 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3232 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3383 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3385 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3392 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3394 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3401 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3403 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N))
[all...] |
| LegalizeTypes.h | 220 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
|
| LegalizeVectorTypes.cpp | 373 EVT DestVT = N->getValueType(0).getVectorElementType();
391 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags());
1938 EVT DestVT = N->getValueType(0);
1940 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1956 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 919 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
926 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
2510 EVT DestVT = Op.getValueType();
2515 if (DestVT == MVT::f16)
2521 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
2526 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2537 if (DestVT == MVT::f32)
2540 assert(DestVT == MVT::f64);
2546 EVT DestVT = Op.getValueType();
2552 if (DestVT == MVT::f16
[all...] |
| SIISelLowering.h | 253 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
|
| SIISelLowering.cpp | 867 EVT DestVT, EVT SrcVT) const {
870 DestVT.getScalarType() == MVT::f32 &&
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 1115 MVT DestVT = TLI->getRegisterType(NewVT);
1116 RegisterVT = DestVT;
1117 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1118 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1579 MVT DestVT = getRegisterType(Context, NewVT);
1580 RegisterVT = DestVT;
1582 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1587 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 2248 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2249 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2254 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2256 AddPromotedToType(Opc, OrigVT, DestVT);
2659 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2660 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2669 EVT DestVT, EVT SrcVT) const {
2670 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2672 return isFPExtFree(DestVT, SrcVT);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 19785 MVT DestVT = Cast.getSimpleValueType();
19795 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM);
19815 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast,
24059 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT;
24061 unsigned DestWidth = DestVT.getScalarSizeInBits();
24065 unsigned DestElts = DestVT.getVectorNumElements();
24074 Curr = DAG.getBitcast(DestVT, Curr);
24077 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr,
[all...] |
